3-D analytical model of the high-voltage interconnection effect for SOI LDMOS

The high-voltage interconnection (HVI) effect induces electric field crowding at the drift region near the source side of power lateral double diffusion MOS (LDMOS). Thus, the electric field profile is deteriorated, and the breakdown characteristic is weakened. This increases the difficulty of device optimization and affects the reliability of the device significantly. Since conventional models based 2-D method can only treat the HVI as a metal layer, therefore, no quantitative analysis can be provided. In order to quantify the impact of the HVI and provide a design scheme for preventing the deterioration in the device's breakdown characteristic, a novel three-dimensional analytical model of the HVI effect for the SOI LDMOS is proposed. By solving the 3-D Poisson's equation, the potential and electric field distribution of the drift region surface are investigated, and the breakdown mechanism is explored quantitatively. The analytical solutions are matched well with the simulation results, which verify the validity of the model. Based on the model, a simple and effective criterion is derived to optimize the structure geometry parameters. The largest width of the HVI metal line is given to prevent the breakdown voltage deterioration.