故障机制驱动的电力电子可靠性模型综述

IF 2.2 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
E. Okafor, D. Huitink
{"title":"故障机制驱动的电力电子可靠性模型综述","authors":"E. Okafor, D. Huitink","doi":"10.1115/1.4055774","DOIUrl":null,"url":null,"abstract":"\n Miniaturization as well as manufacturing processes that electronics devices are subjected to, often results to increase in operational parameters such as current density, temperature, mechanical load, with potential to induce stresses that may be detrimental to device reliability. Past studies have identified some failure mechanisms common to these devices. Examples of these failure mechanisms include fatigue, electromigration, stress induced voiding, corrosion, conduction filament formation and time dependent dielectric breakdown. While some review activities related to reliability model development based on these failure mechanisms can be easily found in literature, to the best of our knowledge, a single review paper, which captures the reliability model progresses made over the past four decades across these failure mechanisms in comparison with Standards such as Joint Electron Device Engineering Council (JEDEC) and Institute for Printed Circuits (IPC) is to the best of our knowledge lacking. To fill this gap, a detailed review of failure mechanism driven reliability models, with emphasis on physics of failure (PoF) for power electronics was carried out in this paper. Although, other failure mechanisms exist, our review is only limited to fatigue, electromigration, stress induced voiding, corrosion, conduction filament formation and time dependent dielectric breakdown. It was found that, most reliability research modelling efforts are yet to be fully integrated into Standards.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":2.2000,"publicationDate":"2022-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Failure Mechanisms Driven Reliability Models for Power Electronics: A Review\",\"authors\":\"E. Okafor, D. Huitink\",\"doi\":\"10.1115/1.4055774\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"\\n Miniaturization as well as manufacturing processes that electronics devices are subjected to, often results to increase in operational parameters such as current density, temperature, mechanical load, with potential to induce stresses that may be detrimental to device reliability. Past studies have identified some failure mechanisms common to these devices. Examples of these failure mechanisms include fatigue, electromigration, stress induced voiding, corrosion, conduction filament formation and time dependent dielectric breakdown. While some review activities related to reliability model development based on these failure mechanisms can be easily found in literature, to the best of our knowledge, a single review paper, which captures the reliability model progresses made over the past four decades across these failure mechanisms in comparison with Standards such as Joint Electron Device Engineering Council (JEDEC) and Institute for Printed Circuits (IPC) is to the best of our knowledge lacking. To fill this gap, a detailed review of failure mechanism driven reliability models, with emphasis on physics of failure (PoF) for power electronics was carried out in this paper. Although, other failure mechanisms exist, our review is only limited to fatigue, electromigration, stress induced voiding, corrosion, conduction filament formation and time dependent dielectric breakdown. It was found that, most reliability research modelling efforts are yet to be fully integrated into Standards.\",\"PeriodicalId\":15663,\"journal\":{\"name\":\"Journal of Electronic Packaging\",\"volume\":\" \",\"pages\":\"\"},\"PeriodicalIF\":2.2000,\"publicationDate\":\"2022-09-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Electronic Packaging\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://doi.org/10.1115/1.4055774\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Electronic Packaging","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1115/1.4055774","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 3

摘要

电子器件所经历的小型化以及制造过程通常会导致操作参数的增加,如电流密度、温度、机械负载,并有可能引发可能对器件可靠性不利的应力。过去的研究已经确定了这些设备常见的一些故障机制。这些失效机制的例子包括疲劳、电迁移、应力引起的空隙、腐蚀、导电丝的形成和时间相关的介电击穿。虽然在文献中可以很容易地找到一些与基于这些失效机制的可靠性模型开发相关的综述活动,但据我们所知,一篇综述论文,据我们所知,与联合电子器件工程委员会(JEDEC)和印刷电路研究所(IPC)等标准相比,它捕捉了过去四十年来在这些故障机制方面取得的可靠性模型进展。为了填补这一空白,本文对失效机制驱动的可靠性模型进行了详细的综述,重点是电力电子的失效物理(PoF)。尽管存在其他失效机制,但我们的综述仅限于疲劳、电迁移、应力引起的空洞、腐蚀、导丝形成和时间相关的介电击穿。研究发现,大多数可靠性研究建模工作尚未完全纳入标准。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Failure Mechanisms Driven Reliability Models for Power Electronics: A Review
Miniaturization as well as manufacturing processes that electronics devices are subjected to, often results to increase in operational parameters such as current density, temperature, mechanical load, with potential to induce stresses that may be detrimental to device reliability. Past studies have identified some failure mechanisms common to these devices. Examples of these failure mechanisms include fatigue, electromigration, stress induced voiding, corrosion, conduction filament formation and time dependent dielectric breakdown. While some review activities related to reliability model development based on these failure mechanisms can be easily found in literature, to the best of our knowledge, a single review paper, which captures the reliability model progresses made over the past four decades across these failure mechanisms in comparison with Standards such as Joint Electron Device Engineering Council (JEDEC) and Institute for Printed Circuits (IPC) is to the best of our knowledge lacking. To fill this gap, a detailed review of failure mechanism driven reliability models, with emphasis on physics of failure (PoF) for power electronics was carried out in this paper. Although, other failure mechanisms exist, our review is only limited to fatigue, electromigration, stress induced voiding, corrosion, conduction filament formation and time dependent dielectric breakdown. It was found that, most reliability research modelling efforts are yet to be fully integrated into Standards.
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来源期刊
Journal of Electronic Packaging
Journal of Electronic Packaging 工程技术-工程:电子与电气
CiteScore
4.90
自引率
6.20%
发文量
44
审稿时长
3 months
期刊介绍: The Journal of Electronic Packaging publishes papers that use experimental and theoretical (analytical and computer-aided) methods, approaches, and techniques to address and solve various mechanical, materials, and reliability problems encountered in the analysis, design, manufacturing, testing, and operation of electronic and photonics components, devices, and systems. Scope: Microsystems packaging; Systems integration; Flexible electronics; Materials with nano structures and in general small scale systems.
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