A low complexity digital frequency calibration with high jitter immunity for ultra-low-power oscillators

Abstract. This paper presents a highly efficient digital frequency calibration method for ultra-low-power oscillators in wireless communication systems. This calibration method locks the ultra-low-power oscillator's output frequency to the reference clock of the wireless transceiver during its send- and receive-state to achieve frequency stability over process variation and temperature drifts. The introduced calibration scheme offers high jitter immunity and short locking periods overcoming frequency calibration errors for typical ultra-low-power oscillator's by utilizing non-linear segmented feedback levels. In measurements the proposed calibration method improves the frequency stability of an ultra-low-power 32 kHz oscillator from 53 to 10 ppm ∘C−1 over a wide temperature range for temperature drifts of less than 1 ∘C s−1 with an estimated power consumption of 185 nW while coping with relocking periods of 7 ms.