{"title":"识别双层SiOx/HfO2栅极电介质堆叠中第一层劣化和失效的简单品质因数","authors":"Andrea Padovani , Paolo La Torraca","doi":"10.1016/j.mee.2023.112080","DOIUrl":null,"url":null,"abstract":"<div><p>Understanding the degradation dynamics and the breakdown sequence of a bilayer high-k (HK) gate dielectric stack is crucial for the improvement of device reliability. We present a new Figure of Merit (FoM), the IL/HK Degradation Index, that depends on fundamental materials properties (the dielectric breakdown strength and the dielectric constant) and can be used to easily and quickly identify the first layer to degrade and fail in a bilayer SiO<sub>2</sub>/HK dielectric stack. Its dependence on IL and HK material parameters is investigated and its validity is demonstrated by means of accurate physics-based simulations of the degradation process. The proposed FoM can be easily used to understand the degradation dynamics of the gate dielectric stack, providing critical insights for device reliability improvement.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.6000,"publicationDate":"2023-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A simple figure of merit to identify the first layer to degrade and fail in dual layer SiOx/HfO2 gate dielectric stacks\",\"authors\":\"Andrea Padovani , Paolo La Torraca\",\"doi\":\"10.1016/j.mee.2023.112080\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>Understanding the degradation dynamics and the breakdown sequence of a bilayer high-k (HK) gate dielectric stack is crucial for the improvement of device reliability. We present a new Figure of Merit (FoM), the IL/HK Degradation Index, that depends on fundamental materials properties (the dielectric breakdown strength and the dielectric constant) and can be used to easily and quickly identify the first layer to degrade and fail in a bilayer SiO<sub>2</sub>/HK dielectric stack. Its dependence on IL and HK material parameters is investigated and its validity is demonstrated by means of accurate physics-based simulations of the degradation process. The proposed FoM can be easily used to understand the degradation dynamics of the gate dielectric stack, providing critical insights for device reliability improvement.</p></div>\",\"PeriodicalId\":18557,\"journal\":{\"name\":\"Microelectronic Engineering\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.6000,\"publicationDate\":\"2023-09-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronic Engineering\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167931723001454\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronic Engineering","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167931723001454","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A simple figure of merit to identify the first layer to degrade and fail in dual layer SiOx/HfO2 gate dielectric stacks
Understanding the degradation dynamics and the breakdown sequence of a bilayer high-k (HK) gate dielectric stack is crucial for the improvement of device reliability. We present a new Figure of Merit (FoM), the IL/HK Degradation Index, that depends on fundamental materials properties (the dielectric breakdown strength and the dielectric constant) and can be used to easily and quickly identify the first layer to degrade and fail in a bilayer SiO2/HK dielectric stack. Its dependence on IL and HK material parameters is investigated and its validity is demonstrated by means of accurate physics-based simulations of the degradation process. The proposed FoM can be easily used to understand the degradation dynamics of the gate dielectric stack, providing critical insights for device reliability improvement.
期刊介绍:
Microelectronic Engineering is the premier nanoprocessing, and nanotechnology journal focusing on fabrication of electronic, photonic, bioelectronic, electromechanic and fluidic devices and systems, and their applications in the broad areas of electronics, photonics, energy, life sciences, and environment. It covers also the expanding interdisciplinary field of "more than Moore" and "beyond Moore" integrated nanoelectronics / photonics and micro-/nano-/bio-systems. Through its unique mixture of peer-reviewed articles, reviews, accelerated publications, short and Technical notes, and the latest research news on key developments, Microelectronic Engineering provides comprehensive coverage of this exciting, interdisciplinary and dynamic new field for researchers in academia and professionals in industry.