Leadfree Sac Solder Materials Characterization At High Strain Rates At Low Test Temperatures And Drop & Shock Simulation Using Input-G Method

Electronics will experience high and low working temperatures during operations, handling, and storage in severe environments applications such as download drilling, aircraft, and transportation. Temperatures in the vehicle underhood applications can range from -65 to +200 °C. Lead-free solder materials continue to evolve under varying thermal workloads. Material characteristics may deteriorate if operating conditions are harsh or heavy. Nonetheless, lead-free solders are susceptible to high strains, which can lead to electronic device failure. A better understanding of solder alloys is needed to ensure reliable operation in harsh environments. New doped solder alloys have recently been created by adding Ni, Co, Au, P, Ga, Cu, and Sb to SnAgCu (SAC) solder alloys to improve mechanical, thermal, and other qualities. SAC-Q has recently been made using Sn-Ag-Cu and the addition of Bi (SAC+Bi). It was discovered that adding dopants to SAC alloys may enhance mechanical characteristics and reduce aging damage. There is no published data on SAC solder alloys after prolonged storage at high strain rates and low functioning temperatures. The materials characterization of SAC (SAC105 and SAC-Q) solder after extended storage at low working temperatures (-65°C-0 °C) and high strain rates (10-75 per sec) is investigated in this article. To characterize the material constitutive behavior, the Anand Viscoplastic model was utilized to derive 9 Anand parameters from recorded Tensile data. The generated 9 Anand parameters were used to validate the Anand model's reliability. A strong correlation was established between experimental data and Anand's predicted data. The Anand parameters were used in a FE framework to simulate drop events for a ball-grid array package on printed circuit board assembly to calculate hysteresis loop and plastic work density. The plastic work per shock event measures the damage progression of the solder interconnects. Thermal aging effects have been studied in terms of the hysteresis loop and the evolution of PWD.