具有自调节阻抗缓冲器的高压低静态电流LDO

IF 1 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC
L. Tian, Zhong Chen, Qinqin Li, Weiheng Wang
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引用次数: 0

摘要

摘要为了提高LDO的整体性能,本文提出了一种带有自调节阻抗缓冲器和带隙放大器的高压LDO低静态电流结构。该带隙放大器可以同时实现基准电压和误差放大器的功能,有效地降低了功耗。采用自调节阻抗缓冲器和电流缓冲器补偿方案,负载电容可小至0.47µF。LDO的工艺为0.18µm,芯片尺寸为0.03 mm2。无负载时,LDO的静态电流消耗为1µA。实验结果表明,线路瞬态响应的超调和欠调均小于30 mV/V。负载稳压约为0.1A,空载时线路稳压约为0.07 mV/V。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High voltage low quiescent current LDO with self-regulation impedance buffer
Abstract To improve the whole characteristic of the LDO, a low quiescent current structure of high voltage LDO with self-regulation impedance buffer and bandgap amplifier is presented in this paper. With the bandgap amplifier proposed, the function of voltage reference and error amplifier can be achieved simultaneously, which can efficiently reduce the consumption. The load capacitor can be as small as 0.47µF by using the self-regulation impedance buffer and current buffer compensation scheme. The LDO has been implemented in a 0.18 µm process with die size 0.03 mm2 . Without the load, the consumption quiescent current of the LDO is 1 µA. Experimental result shows that the overshoot and undershoot of line transient response are less than 30 mV/V. The load regulation is about 0.1A, and line regulation is about 0.07 mV/V at no load condition.
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来源期刊
Journal of Electrical Engineering-elektrotechnicky Casopis
Journal of Electrical Engineering-elektrotechnicky Casopis 工程技术-工程:电子与电气
CiteScore
1.70
自引率
12.50%
发文量
40
审稿时长
6-12 weeks
期刊介绍: The joint publication of the Slovak University of Technology, Faculty of Electrical Engineering and Information Technology, and of the Slovak Academy of Sciences, Institute of Electrical Engineering, is a wide-scope journal published bimonthly and comprising. -Automation and Control- Computer Engineering- Electronics and Microelectronics- Electro-physics and Electromagnetism- Material Science- Measurement and Metrology- Power Engineering and Energy Conversion- Signal Processing and Telecommunications
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