High-Speed Low-Power Approach for Implementation of 8B/10B Encoder for High-Speed Communications

In this paper, the design methodology for a high-speed 8B/10B encoding architecture has been discussed. By means of the new truth table and with the help of Pass-Transistor Logic (PTL), a new structure has been designed in CMOS technology, which shows a superior speed performance. Also, power consumption is optimized because of careful design considerations. These features, along with the simplicity of the employed circuitry are the quality of this work to be repeatedly used in high-speed communication systems. The design process has been explained in detail so that the idea can completely be understood. Moreover, the proposed structure has been demonstrated in the circuit level for better clarification. Post-layout simulation results for TSMC 0.18µm standard CMOS technology depict the correct behavior of the proposed architecture whilst the power consumption is 1.64mW from 1.8v power supply.