Ranhui Liu,Yuansheng Zhao,Shenwu Zhu,Tianyue Fu,Zhiyu Wang,Yuzhe Zhu,Chao Wang,Lianmao Peng,Qianlan Hu
{"title":"单片3D堆叠碳纳米管/铟锡氧化物互补晶体管用于高频逻辑和感测放大器与存储器集成","authors":"Ranhui Liu,Yuansheng Zhao,Shenwu Zhu,Tianyue Fu,Zhiyu Wang,Yuzhe Zhu,Chao Wang,Lianmao Peng,Qianlan Hu","doi":"10.1021/acsnano.6c11662","DOIUrl":null,"url":null,"abstract":"Complementary field-effect transistors (CFETs) maximize 3D integration density but face two fundamental bottlenecks: the stringent thermal budget of silicon-based sequential stacking and the inherent electrical mismatches in homogeneous material systems. To overcome these challenges, we demonstrate a monolithic 3D-stacked heterogeneous CFET architecture integrating back-end-of-line (BEOL)-compatible p-type carbon nanotube (CNT) and n-type indium–tin–oxide (ITO) channels. Both materials exhibit high carrier mobility and low-temperature process, which simultaneously resolve the bipolar transport disparity and mitigate thermal degradation. Consequently, the resulting CFET inverters exhibit favorable statistical uniformity and symmetric transfer characteristics, enabling the fabrication of versatile logic gates. Besides, a 5-stage ring oscillator (RO) achieves a high frequency of 334 MHz, with a 0.3 ns stage delay, demonstrating potential applications of CFET in high-speed digital circuits. Furthermore, bridging logic and memory, a CFET-based sense amplifier (SA) is integrated with an ITO-based planar capacitorless (2T0C) dynamic random-access memory (DRAM) cell. This hybrid system achieves data write/read operations and signal amplification, providing an architectural platform for next-generation ultradense 3D logic and memory systems.","PeriodicalId":21,"journal":{"name":"ACS Nano","volume":"73 1","pages":""},"PeriodicalIF":17.3000,"publicationDate":"2026-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Monolithic 3D Stacked Carbon Nanotube/Indium–Tin–Oxide Complementary Transistors for High-Frequency Logic and Sense Amplifier Integration with Memory\",\"authors\":\"Ranhui Liu,Yuansheng Zhao,Shenwu Zhu,Tianyue Fu,Zhiyu Wang,Yuzhe Zhu,Chao Wang,Lianmao Peng,Qianlan Hu\",\"doi\":\"10.1021/acsnano.6c11662\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Complementary field-effect transistors (CFETs) maximize 3D integration density but face two fundamental bottlenecks: the stringent thermal budget of silicon-based sequential stacking and the inherent electrical mismatches in homogeneous material systems. To overcome these challenges, we demonstrate a monolithic 3D-stacked heterogeneous CFET architecture integrating back-end-of-line (BEOL)-compatible p-type carbon nanotube (CNT) and n-type indium–tin–oxide (ITO) channels. Both materials exhibit high carrier mobility and low-temperature process, which simultaneously resolve the bipolar transport disparity and mitigate thermal degradation. Consequently, the resulting CFET inverters exhibit favorable statistical uniformity and symmetric transfer characteristics, enabling the fabrication of versatile logic gates. Besides, a 5-stage ring oscillator (RO) achieves a high frequency of 334 MHz, with a 0.3 ns stage delay, demonstrating potential applications of CFET in high-speed digital circuits. Furthermore, bridging logic and memory, a CFET-based sense amplifier (SA) is integrated with an ITO-based planar capacitorless (2T0C) dynamic random-access memory (DRAM) cell. This hybrid system achieves data write/read operations and signal amplification, providing an architectural platform for next-generation ultradense 3D logic and memory systems.\",\"PeriodicalId\":21,\"journal\":{\"name\":\"ACS Nano\",\"volume\":\"73 1\",\"pages\":\"\"},\"PeriodicalIF\":17.3000,\"publicationDate\":\"2026-10-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ACS Nano\",\"FirstCategoryId\":\"88\",\"ListUrlMain\":\"https://doi.org/10.1021/acsnano.6c11662\",\"RegionNum\":1,\"RegionCategory\":\"材料科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"CHEMISTRY, MULTIDISCIPLINARY\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACS Nano","FirstCategoryId":"88","ListUrlMain":"https://doi.org/10.1021/acsnano.6c11662","RegionNum":1,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"CHEMISTRY, MULTIDISCIPLINARY","Score":null,"Total":0}
Monolithic 3D Stacked Carbon Nanotube/Indium–Tin–Oxide Complementary Transistors for High-Frequency Logic and Sense Amplifier Integration with Memory
Complementary field-effect transistors (CFETs) maximize 3D integration density but face two fundamental bottlenecks: the stringent thermal budget of silicon-based sequential stacking and the inherent electrical mismatches in homogeneous material systems. To overcome these challenges, we demonstrate a monolithic 3D-stacked heterogeneous CFET architecture integrating back-end-of-line (BEOL)-compatible p-type carbon nanotube (CNT) and n-type indium–tin–oxide (ITO) channels. Both materials exhibit high carrier mobility and low-temperature process, which simultaneously resolve the bipolar transport disparity and mitigate thermal degradation. Consequently, the resulting CFET inverters exhibit favorable statistical uniformity and symmetric transfer characteristics, enabling the fabrication of versatile logic gates. Besides, a 5-stage ring oscillator (RO) achieves a high frequency of 334 MHz, with a 0.3 ns stage delay, demonstrating potential applications of CFET in high-speed digital circuits. Furthermore, bridging logic and memory, a CFET-based sense amplifier (SA) is integrated with an ITO-based planar capacitorless (2T0C) dynamic random-access memory (DRAM) cell. This hybrid system achieves data write/read operations and signal amplification, providing an architectural platform for next-generation ultradense 3D logic and memory systems.
期刊介绍:
ACS Nano, published monthly, serves as an international forum for comprehensive articles on nanoscience and nanotechnology research at the intersections of chemistry, biology, materials science, physics, and engineering. The journal fosters communication among scientists in these communities, facilitating collaboration, new research opportunities, and advancements through discoveries. ACS Nano covers synthesis, assembly, characterization, theory, and simulation of nanostructures, nanobiotechnology, nanofabrication, methods and tools for nanoscience and nanotechnology, and self- and directed-assembly. Alongside original research articles, it offers thorough reviews, perspectives on cutting-edge research, and discussions envisioning the future of nanoscience and nanotechnology.