Hysteresis Transformation and Memristor Design Framework for Two-Dimensional Materials for Neuromorphic Computing:Physics-Based Charge-Diffusion Modelling and Machine Learning

Hysteresis is the defining electrical signature of memristive dynamics and underpins the history-dependent conductance required for artificial synapses and neuromorphic computing. However, unlike conventional passive electronic components, memristive devices lack a universally accepted framework for quantitatively characterizing and reporting their diverse hysteretic responses, making cross-device comparison and systematic engineering difficult. For lateral 2D-material memristors, this challenge is amplified by the strong dependence of hysteresis on coupled material, transport, and interface parameters, yet a unified quantitative map connecting these parameters to hysteresis emergence, loop classes, figures of merit (FoMs), and controllable transformations between hysteresis types remains unavailable. In this work, we develop a physics-informed, data-driven hysteresis engineering framework for 2D lateral memristors using a coupled transport model that solves the drift–diffusion equations for the quasi-Fermi potentials of charge carriers, the electrostatic potential from Poisson’s equation, and Schottky barrier modulation at a specified temperature. From ∼10,000 simulations across seven input parameters, we identified that ∼13.3% of configurations exhibit hysteresis, clustering into six loop types. We define 11 FoMs (loop area, memory ratios, nonlinearity, collapse/stationary indicators) and map their type-specific statistical distributions. Sensitivity and correlation analyses identify dominant knobs and enable loop transformations by tuning electrode spacing, vacancy mobility, barrier height, and scan rate, in agreement with experimental reports. We establish more than 500 relationships between input material/device properties and output hysteresis FoMs. Machine-learning models achieve 96.5% accuracy in hysteresis prediction and 76.38% accuracy in hysteresis loop-type classification. This work provides a framework for hysteresis engineering in memristive devices, enabling rapid screening and inverse design for next-generation computing applications.