用双向规划解决高效QLC固态硬盘的灰色码困境

IF 3.6 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Yi Wang;Shaoqi Li;Yongbiao Zhu;Tianyu Wang;Chenlin Ma;Rui Mao;Zili Shao
{"title":"用双向规划解决高效QLC固态硬盘的灰色码困境","authors":"Yi Wang;Shaoqi Li;Yongbiao Zhu;Tianyu Wang;Chenlin Ma;Rui Mao;Zili Shao","doi":"10.1109/TCAD.2025.3637010","DOIUrl":null,"url":null,"abstract":"Quad-level cell (QLC)NAND flash is widely adopted in modern storage systems. By trading off read/write performance for storage density through a “time-for-space” approach, QLC enables ultrahigh storage capacity. To mitigate performance degradation, Gray code and the two-step programming (TSP) algorithm are used. However, Gray code also has limitations: multiple Gray codes (MGCs) incur circuit overhead, while a single Gray code causes extra I/O latency overhead. This paradox seems unsolvable at first glance, requiring an innovative solution that maintains I/O performance without additional circuit overhead. A promising solution lies in selecting an appropriate Gray code and preventing hot data placement on slow physical pages. This article proposes BDP, a novel bidirectional programming scheme that adopts a single Gray code to fit both traditional (forward) and reverse programming directions based on TSP. The objective of BDP is to resolve the inherent contradiction between I/O performance preservation and implementation overhead. BDP optimizes the system performance through hardware/software co-design. At the hardware level, a fixed Gray code is employed to avoid additional circuit complexity. At the software level, two strategies (i.e., hotness-aware data allocation and background data migration) are proposed to further mitigate the misplacement of hot data on slow pages in QLC solid state drives (SSDs). The experimental results demonstrate that BDP significantly reduces the allocation of hot data to slow pages and enhances overall I/O performance compared with representative schemes.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3401-3414"},"PeriodicalIF":3.6000,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Resolving Gray Code Dilemma With Bidirectional Programming for Efficient QLC SSDs\",\"authors\":\"Yi Wang;Shaoqi Li;Yongbiao Zhu;Tianyu Wang;Chenlin Ma;Rui Mao;Zili Shao\",\"doi\":\"10.1109/TCAD.2025.3637010\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Quad-level cell (QLC)NAND flash is widely adopted in modern storage systems. By trading off read/write performance for storage density through a “time-for-space” approach, QLC enables ultrahigh storage capacity. To mitigate performance degradation, Gray code and the two-step programming (TSP) algorithm are used. However, Gray code also has limitations: multiple Gray codes (MGCs) incur circuit overhead, while a single Gray code causes extra I/O latency overhead. This paradox seems unsolvable at first glance, requiring an innovative solution that maintains I/O performance without additional circuit overhead. A promising solution lies in selecting an appropriate Gray code and preventing hot data placement on slow physical pages. This article proposes BDP, a novel bidirectional programming scheme that adopts a single Gray code to fit both traditional (forward) and reverse programming directions based on TSP. The objective of BDP is to resolve the inherent contradiction between I/O performance preservation and implementation overhead. BDP optimizes the system performance through hardware/software co-design. At the hardware level, a fixed Gray code is employed to avoid additional circuit complexity. At the software level, two strategies (i.e., hotness-aware data allocation and background data migration) are proposed to further mitigate the misplacement of hot data on slow pages in QLC solid state drives (SSDs). The experimental results demonstrate that BDP significantly reduces the allocation of hot data to slow pages and enhances overall I/O performance compared with representative schemes.\",\"PeriodicalId\":13251,\"journal\":{\"name\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"volume\":\"45 7\",\"pages\":\"3401-3414\"},\"PeriodicalIF\":3.6000,\"publicationDate\":\"2026-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11268502/\",\"RegionNum\":3,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"2025/11/25 0:00:00\",\"PubModel\":\"Epub\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/11268502/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2025/11/25 0:00:00","PubModel":"Epub","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

摘要

四电平单元(QLC)NAND闪存在现代存储系统中被广泛采用。通过“时间换空间”的方法来权衡读写性能和存储密度,QLC实现了超高的存储容量。为了减少性能下降,采用了Gray编码和两步规划(TSP)算法。然而,Gray码也有局限性:多个Gray码(MGCs)会导致电路开销,而单个Gray码会导致额外的I/O延迟开销。乍一看,这个矛盾似乎无法解决,需要一种创新的解决方案,在不增加电路开销的情况下保持I/O性能。一个很有前途的解决方案是选择适当的Gray代码并防止在缓慢的物理页面上放置热数据。本文提出了一种基于TSP的双向规划方案BDP,它采用单一的Gray码来适应传统的(正向)和反向规划方向。BDP的目标是解决I/O性能保持和实现开销之间的内在矛盾。BDP通过硬件/软件协同设计优化系统性能。在硬件层,采用固定的格雷码,以避免额外的电路复杂性。在软件层面,提出了两种策略(即热感知数据分配和后台数据迁移)来进一步缓解QLC固态硬盘(ssd)中热数据在慢速页面上的错位。实验结果表明,与代表性方案相比,BDP显著减少了对慢速页面的热数据分配,提高了整体I/O性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Resolving Gray Code Dilemma With Bidirectional Programming for Efficient QLC SSDs
Quad-level cell (QLC)NAND flash is widely adopted in modern storage systems. By trading off read/write performance for storage density through a “time-for-space” approach, QLC enables ultrahigh storage capacity. To mitigate performance degradation, Gray code and the two-step programming (TSP) algorithm are used. However, Gray code also has limitations: multiple Gray codes (MGCs) incur circuit overhead, while a single Gray code causes extra I/O latency overhead. This paradox seems unsolvable at first glance, requiring an innovative solution that maintains I/O performance without additional circuit overhead. A promising solution lies in selecting an appropriate Gray code and preventing hot data placement on slow physical pages. This article proposes BDP, a novel bidirectional programming scheme that adopts a single Gray code to fit both traditional (forward) and reverse programming directions based on TSP. The objective of BDP is to resolve the inherent contradiction between I/O performance preservation and implementation overhead. BDP optimizes the system performance through hardware/software co-design. At the hardware level, a fixed Gray code is employed to avoid additional circuit complexity. At the software level, two strategies (i.e., hotness-aware data allocation and background data migration) are proposed to further mitigate the misplacement of hot data on slow pages in QLC solid state drives (SSDs). The experimental results demonstrate that BDP significantly reduces the allocation of hot data to slow pages and enhances overall I/O performance compared with representative schemes.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信
小红书