{"title":"PMTV PUF:具有温度和电压波动耐受性的功率感知和ml安全PUF","authors":"Abolfazl Rajaiyan;Yas Hosseini Tehrani;Seyed Mojtaba Atarodi","doi":"10.1109/TCAD.2025.3634304","DOIUrl":null,"url":null,"abstract":"Security of data transmission is one of the main challenges in the Internet of Things (IoT) networks. One of the main solutions to ensure security in these networks is physically unclonable functions (PUFs). The performance of the PUFs is highly dependent on voltage and temperature. Moreover, this solution can be successfully attacked by machine learning (ML) approaches. Detecting the possibility of an attack helps in preventing it. In this article, a novel PUF (PMTV PUF) is presented. The proposed circuit uses a pipeline structure. This structure improves the reliability of the PUF under different voltages and temperatures. Pipeline architecture is also used to resist ML attacks. Challenge obfuscation is applied in the pipeline stages. This makes it harder for ML models to learn the behavior. In addition, new techniques for measuring system power consumption are used. These techniques help detect and prevent potential ML attacks. The proposed PMTV PUF circuit is implemented on a Xilinx Zynq 7 FPGA with the proposed power measurement circuit as an extension. Experimental results show the great performance of the responses. The bit error rate (BER) is <inline-formula> <tex-math>$3.17 \\times 10^{-10}$ </tex-math></inline-formula> (at <inline-formula> <tex-math>$150~^{\\circ }$ </tex-math></inline-formula>C with a 1.32-V supply voltage), the uniformity is 50.12%, and the uniqueness is 49.87%. In conventional architectures, the average system vulnerability against ML attacks is approximately <inline-formula> <tex-math>$\\mathbf {9 0 \\%}$ </tex-math></inline-formula>. In the proposed architecture, this vulnerability has been reduced to 50.23%. According to the obtained result, the proposed system not only has high reliability but also possesses the ability to detect and prevent potential ML attacks.","PeriodicalId":13251,"journal":{"name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","volume":"45 7","pages":"3540-3548"},"PeriodicalIF":3.6000,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"PMTV PUF: Power-Aware and ML-Secure PUF With Tolerance to Temperature and Voltage Fluctuations\",\"authors\":\"Abolfazl Rajaiyan;Yas Hosseini Tehrani;Seyed Mojtaba Atarodi\",\"doi\":\"10.1109/TCAD.2025.3634304\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Security of data transmission is one of the main challenges in the Internet of Things (IoT) networks. One of the main solutions to ensure security in these networks is physically unclonable functions (PUFs). The performance of the PUFs is highly dependent on voltage and temperature. Moreover, this solution can be successfully attacked by machine learning (ML) approaches. Detecting the possibility of an attack helps in preventing it. In this article, a novel PUF (PMTV PUF) is presented. The proposed circuit uses a pipeline structure. This structure improves the reliability of the PUF under different voltages and temperatures. Pipeline architecture is also used to resist ML attacks. Challenge obfuscation is applied in the pipeline stages. This makes it harder for ML models to learn the behavior. In addition, new techniques for measuring system power consumption are used. These techniques help detect and prevent potential ML attacks. The proposed PMTV PUF circuit is implemented on a Xilinx Zynq 7 FPGA with the proposed power measurement circuit as an extension. Experimental results show the great performance of the responses. The bit error rate (BER) is <inline-formula> <tex-math>$3.17 \\\\times 10^{-10}$ </tex-math></inline-formula> (at <inline-formula> <tex-math>$150~^{\\\\circ }$ </tex-math></inline-formula>C with a 1.32-V supply voltage), the uniformity is 50.12%, and the uniqueness is 49.87%. In conventional architectures, the average system vulnerability against ML attacks is approximately <inline-formula> <tex-math>$\\\\mathbf {9 0 \\\\%}$ </tex-math></inline-formula>. In the proposed architecture, this vulnerability has been reduced to 50.23%. According to the obtained result, the proposed system not only has high reliability but also possesses the ability to detect and prevent potential ML attacks.\",\"PeriodicalId\":13251,\"journal\":{\"name\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"volume\":\"45 7\",\"pages\":\"3540-3548\"},\"PeriodicalIF\":3.6000,\"publicationDate\":\"2026-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11251339/\",\"RegionNum\":3,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"2025/11/18 0:00:00\",\"PubModel\":\"Epub\",\"JCR\":\"Q2\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/11251339/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2025/11/18 0:00:00","PubModel":"Epub","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
PMTV PUF: Power-Aware and ML-Secure PUF With Tolerance to Temperature and Voltage Fluctuations
Security of data transmission is one of the main challenges in the Internet of Things (IoT) networks. One of the main solutions to ensure security in these networks is physically unclonable functions (PUFs). The performance of the PUFs is highly dependent on voltage and temperature. Moreover, this solution can be successfully attacked by machine learning (ML) approaches. Detecting the possibility of an attack helps in preventing it. In this article, a novel PUF (PMTV PUF) is presented. The proposed circuit uses a pipeline structure. This structure improves the reliability of the PUF under different voltages and temperatures. Pipeline architecture is also used to resist ML attacks. Challenge obfuscation is applied in the pipeline stages. This makes it harder for ML models to learn the behavior. In addition, new techniques for measuring system power consumption are used. These techniques help detect and prevent potential ML attacks. The proposed PMTV PUF circuit is implemented on a Xilinx Zynq 7 FPGA with the proposed power measurement circuit as an extension. Experimental results show the great performance of the responses. The bit error rate (BER) is $3.17 \times 10^{-10}$ (at $150~^{\circ }$ C with a 1.32-V supply voltage), the uniformity is 50.12%, and the uniqueness is 49.87%. In conventional architectures, the average system vulnerability against ML attacks is approximately $\mathbf {9 0 \%}$ . In the proposed architecture, this vulnerability has been reduced to 50.23%. According to the obtained result, the proposed system not only has high reliability but also possesses the ability to detect and prevent potential ML attacks.
期刊介绍:
The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.