{"title":"基于IC布局文件的晶体管级三维热分析","authors":"Kaili Ding, Kai Sun, Maozheng Liu, Haihang Cui","doi":"10.1007/s10825-026-02546-z","DOIUrl":null,"url":null,"abstract":"<div><p>With the rapid advancement of chip integration adhering to Moore’s Law, local hotspots within the chip have emerged as critical factors influencing chip functionality and reliability. Traditional research into circuit-level chip thermal distribution remains focused on 2D planar structure analysis. To address the absence of 3D structure thermal analysis at circuit level, a novel methodology for 3D chip thermal analysis at semiconductor transistor level is proposed. By utilizing the chip layout file (GDSII file), the 3D structure is constructed and exported in STP format, compatible with COMSOL, which is a COMSOL. This enables the analysis of transistor-level 3D thermal distribution. The effectiveness of this method is validated through a practical case study involving circuit-level chip thermal analysis.</p></div>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":"25 3","pages":""},"PeriodicalIF":2.5000,"publicationDate":"2026-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"3D thermal analysis at transistor level based on IC layout files\",\"authors\":\"Kaili Ding, Kai Sun, Maozheng Liu, Haihang Cui\",\"doi\":\"10.1007/s10825-026-02546-z\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>With the rapid advancement of chip integration adhering to Moore’s Law, local hotspots within the chip have emerged as critical factors influencing chip functionality and reliability. Traditional research into circuit-level chip thermal distribution remains focused on 2D planar structure analysis. To address the absence of 3D structure thermal analysis at circuit level, a novel methodology for 3D chip thermal analysis at semiconductor transistor level is proposed. By utilizing the chip layout file (GDSII file), the 3D structure is constructed and exported in STP format, compatible with COMSOL, which is a COMSOL. This enables the analysis of transistor-level 3D thermal distribution. The effectiveness of this method is validated through a practical case study involving circuit-level chip thermal analysis.</p></div>\",\"PeriodicalId\":620,\"journal\":{\"name\":\"Journal of Computational Electronics\",\"volume\":\"25 3\",\"pages\":\"\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2026-04-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Computational Electronics\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://link.springer.com/article/10.1007/s10825-026-02546-z\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Computational Electronics","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10825-026-02546-z","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
3D thermal analysis at transistor level based on IC layout files
With the rapid advancement of chip integration adhering to Moore’s Law, local hotspots within the chip have emerged as critical factors influencing chip functionality and reliability. Traditional research into circuit-level chip thermal distribution remains focused on 2D planar structure analysis. To address the absence of 3D structure thermal analysis at circuit level, a novel methodology for 3D chip thermal analysis at semiconductor transistor level is proposed. By utilizing the chip layout file (GDSII file), the 3D structure is constructed and exported in STP format, compatible with COMSOL, which is a COMSOL. This enables the analysis of transistor-level 3D thermal distribution. The effectiveness of this method is validated through a practical case study involving circuit-level chip thermal analysis.
期刊介绍：
he Journal of Computational Electronics brings together research on all aspects of modeling and simulation of modern electronics. This includes optical, electronic, mechanical, and quantum mechanical aspects, as well as research on the underlying mathematical algorithms and computational details. The related areas of energy conversion/storage and of molecular and biological systems, in which the thrust is on the charge transport, electronic, mechanical, and optical properties, are also covered.
In particular, we encourage manuscripts dealing with device simulation; with optical and optoelectronic systems and photonics; with energy storage (e.g. batteries, fuel cells) and harvesting (e.g. photovoltaic), with simulation of circuits, VLSI layout, logic and architecture (based on, for example, CMOS devices, quantum-cellular automata, QBITs, or single-electron transistors); with electromagnetic simulations (such as microwave electronics and components); or with molecular and biological systems. However, in all these cases, the submitted manuscripts should explicitly address the electronic properties of the relevant systems, materials, or devices and/or present novel contributions to the physical models, computational strategies, or numerical algorithms.
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