{"title":"使用基于soa的光交换和监控通道FPGA控制的时间敏感应用的动态、低延迟城域接入网络架构","authors":"Henrique Freire Santana;Ali Mefleh;Nicola Calabretta","doi":"10.1364/JOCN.564881","DOIUrl":null,"url":null,"abstract":"This work presents a metro-access network architecture designed to meet the stringent requirements of time-sensitive applications in emerging 5G and 6G networks. The proposed architecture leverages semiconductor optical amplifier-based optical add-drop multiplexers and FPGA-based controllers to enable dynamic, low-latency operation suitable for applications with critical latency and jitter demands. We introduce a control plane protocol that allows for deterministic time-slotted resource reservation, ensuring transparent optical switching and minimizing latency. We validate the architecture through a prototype implementation in a ring network topology, demonstrating latency-bounded operation. Experimental results show that the network achieves sub-microsecond reconfiguration times and stable latency performance, with transparency crossing up to six nodes and a data recovery time of 100 ns at <tex>${-}{17}\\;{\\rm dBm}$</tex>, making the architecture a potential solution for federated computing and edge cloud scenarios.","PeriodicalId":50103,"journal":{"name":"Journal of Optical Communications and Networking","volume":"17 11","pages":"995-1005"},"PeriodicalIF":4.3000,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Dynamic, low-latency metro-access network architecture for time-sensitive applications using SOA-based optical switching and supervisory channel FPGA control\",\"authors\":\"Henrique Freire Santana;Ali Mefleh;Nicola Calabretta\",\"doi\":\"10.1364/JOCN.564881\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents a metro-access network architecture designed to meet the stringent requirements of time-sensitive applications in emerging 5G and 6G networks. The proposed architecture leverages semiconductor optical amplifier-based optical add-drop multiplexers and FPGA-based controllers to enable dynamic, low-latency operation suitable for applications with critical latency and jitter demands. We introduce a control plane protocol that allows for deterministic time-slotted resource reservation, ensuring transparent optical switching and minimizing latency. We validate the architecture through a prototype implementation in a ring network topology, demonstrating latency-bounded operation. Experimental results show that the network achieves sub-microsecond reconfiguration times and stable latency performance, with transparency crossing up to six nodes and a data recovery time of 100 ns at <tex>${-}{17}\\\\;{\\\\rm dBm}$</tex>, making the architecture a potential solution for federated computing and edge cloud scenarios.\",\"PeriodicalId\":50103,\"journal\":{\"name\":\"Journal of Optical Communications and Networking\",\"volume\":\"17 11\",\"pages\":\"995-1005\"},\"PeriodicalIF\":4.3000,\"publicationDate\":\"2025-10-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Optical Communications and Networking\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11203825/\",\"RegionNum\":2,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Optical Communications and Networking","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/11203825/","RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Dynamic, low-latency metro-access network architecture for time-sensitive applications using SOA-based optical switching and supervisory channel FPGA control
This work presents a metro-access network architecture designed to meet the stringent requirements of time-sensitive applications in emerging 5G and 6G networks. The proposed architecture leverages semiconductor optical amplifier-based optical add-drop multiplexers and FPGA-based controllers to enable dynamic, low-latency operation suitable for applications with critical latency and jitter demands. We introduce a control plane protocol that allows for deterministic time-slotted resource reservation, ensuring transparent optical switching and minimizing latency. We validate the architecture through a prototype implementation in a ring network topology, demonstrating latency-bounded operation. Experimental results show that the network achieves sub-microsecond reconfiguration times and stable latency performance, with transparency crossing up to six nodes and a data recovery time of 100 ns at ${-}{17}\;{\rm dBm}$, making the architecture a potential solution for federated computing and edge cloud scenarios.
期刊介绍:
The scope of the Journal includes advances in the state-of-the-art of optical networking science, technology, and engineering. Both theoretical contributions (including new techniques, concepts, analyses, and economic studies) and practical contributions (including optical networking experiments, prototypes, and new applications) are encouraged. Subareas of interest include the architecture and design of optical networks, optical network survivability and security, software-defined optical networking, elastic optical networks, data and control plane advances, network management related innovation, and optical access networks. Enabling technologies and their applications are suitable topics only if the results are shown to directly impact optical networking beyond simple point-to-point networks.