Yihao Zhang, Kangqi An, Yi Li, Bowen Tian, Zelong Qu, Peng Sun, Bin Zhao, Yumeng Cai, Zhibin Zhao
{"title":"并联芯片集成电流监测的6.5 kV/100A低电感SiC MOSFET功率模块","authors":"Yihao Zhang, Kangqi An, Yi Li, Bowen Tian, Zelong Qu, Peng Sun, Bin Zhao, Yumeng Cai, Zhibin Zhao","doi":"10.1049/pel2.70116","DOIUrl":null,"url":null,"abstract":"<p>To monitor the operating status and fault behaviour of power modules, this paper proposes a 6.5 kV/100 A silicon carbide (SiC) MOSFET power module capable of monitoring the drain currents of parallel-connected chips. The design combines three key innovations: (1) A structure and integration method for a four-channel printed circuit board (PCB) Rogowski coil used in high-voltage SiC power modules is proposed, exhibiting excellent anti-interference; (2) To reduce both the total module parasitic inductance and package-induced inductance imbalance, a symmetrical layout with pin-type terminals was proposed. (3) A field control method for the 6.5 kV power module is proposed, based on adjusting ceramic thickness and copper layer spacing at the triple junction. The module was fabricated to validate the effectiveness of these innovations. Under 15 kV DC and 50 Hz square-wave voltage conditions, no repetitive partial discharge exceeding 10 pC or leakage current above 1 µA was observed. The power loop parasitic inductance was measured as approximately 14.94 nH using an impedance analyser. Finally, the static and dynamic characteristics of the module were validated through static parameter analysis and double-pulse testing. The integrated PCB Rogowski coils monitored the drain current through each chip during double-pulse tests, showing good agreement with measurements from the commercial high-bandwidth Pearson coil.</p>","PeriodicalId":56302,"journal":{"name":"IET Power Electronics","volume":"18 1","pages":""},"PeriodicalIF":1.9000,"publicationDate":"2025-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/pel2.70116","citationCount":"0","resultStr":"{\"title\":\"A 6.5 kV/100A Low-Inductance SiC MOSFET Power Module With Integrated Current Monitoring for Parallel Chips\",\"authors\":\"Yihao Zhang, Kangqi An, Yi Li, Bowen Tian, Zelong Qu, Peng Sun, Bin Zhao, Yumeng Cai, Zhibin Zhao\",\"doi\":\"10.1049/pel2.70116\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p>To monitor the operating status and fault behaviour of power modules, this paper proposes a 6.5 kV/100 A silicon carbide (SiC) MOSFET power module capable of monitoring the drain currents of parallel-connected chips. The design combines three key innovations: (1) A structure and integration method for a four-channel printed circuit board (PCB) Rogowski coil used in high-voltage SiC power modules is proposed, exhibiting excellent anti-interference; (2) To reduce both the total module parasitic inductance and package-induced inductance imbalance, a symmetrical layout with pin-type terminals was proposed. (3) A field control method for the 6.5 kV power module is proposed, based on adjusting ceramic thickness and copper layer spacing at the triple junction. The module was fabricated to validate the effectiveness of these innovations. Under 15 kV DC and 50 Hz square-wave voltage conditions, no repetitive partial discharge exceeding 10 pC or leakage current above 1 µA was observed. The power loop parasitic inductance was measured as approximately 14.94 nH using an impedance analyser. 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A 6.5 kV/100A Low-Inductance SiC MOSFET Power Module With Integrated Current Monitoring for Parallel Chips
To monitor the operating status and fault behaviour of power modules, this paper proposes a 6.5 kV/100 A silicon carbide (SiC) MOSFET power module capable of monitoring the drain currents of parallel-connected chips. The design combines three key innovations: (1) A structure and integration method for a four-channel printed circuit board (PCB) Rogowski coil used in high-voltage SiC power modules is proposed, exhibiting excellent anti-interference; (2) To reduce both the total module parasitic inductance and package-induced inductance imbalance, a symmetrical layout with pin-type terminals was proposed. (3) A field control method for the 6.5 kV power module is proposed, based on adjusting ceramic thickness and copper layer spacing at the triple junction. The module was fabricated to validate the effectiveness of these innovations. Under 15 kV DC and 50 Hz square-wave voltage conditions, no repetitive partial discharge exceeding 10 pC or leakage current above 1 µA was observed. The power loop parasitic inductance was measured as approximately 14.94 nH using an impedance analyser. Finally, the static and dynamic characteristics of the module were validated through static parameter analysis and double-pulse testing. The integrated PCB Rogowski coils monitored the drain current through each chip during double-pulse tests, showing good agreement with measurements from the commercial high-bandwidth Pearson coil.
期刊介绍:
IET Power Electronics aims to attract original research papers, short communications, review articles and power electronics related educational studies. The scope covers applications and technologies in the field of power electronics with special focus on cost-effective, efficient, power dense, environmental friendly and robust solutions, which includes:
Applications:
Electric drives/generators, renewable energy, industrial and consumable applications (including lighting, welding, heating, sub-sea applications, drilling and others), medical and military apparatus, utility applications, transport and space application, energy harvesting, telecommunications, energy storage management systems, home appliances.
Technologies:
Circuits: all type of converter topologies for low and high power applications including but not limited to: inverter, rectifier, dc/dc converter, power supplies, UPS, ac/ac converter, resonant converter, high frequency converter, hybrid converter, multilevel converter, power factor correction circuits and other advanced topologies.
Components and Materials: switching devices and their control, inductors, sensors, transformers, capacitors, resistors, thermal management, filters, fuses and protection elements and other novel low-cost efficient components/materials.
Control: techniques for controlling, analysing, modelling and/or simulation of power electronics circuits and complete power electronics systems.
Design/Manufacturing/Testing: new multi-domain modelling, assembling and packaging technologies, advanced testing techniques.
Environmental Impact: Electromagnetic Interference (EMI) reduction techniques, Electromagnetic Compatibility (EMC), limiting acoustic noise and vibration, recycling techniques, use of non-rare material.
Education: teaching methods, programme and course design, use of technology in power electronics teaching, virtual laboratory and e-learning and fields within the scope of interest.
Special Issues. Current Call for papers:
Harmonic Mitigation Techniques and Grid Robustness in Power Electronic-Based Power Systems - https://digital-library.theiet.org/files/IET_PEL_CFP_HMTGRPEPS.pdf