Enhanced functional verification models that ensure the full functionality of an A-PLL device

Functional verification of analog devices has become a crucial step in validating mixed-signal SoCs. Waiting for the completion of the analog transistor level can delay time-to-market, as digital verification engineers need to ensure both analog and digital systems function correctly when integrated. Given the availability of efficient, reusable, and reliable digital functional verification methodologies — such as Constrained Random Verification (CRV), functional coverage, assertions/checkers, and Universal Verification Methodology (UVM) — this paper explores how these approaches can be applied to an analog-modeled Device Under Test (DUT) to guarantee its functional correctness. The DUT in question is an Analog Phase-Locked Loop (APLL), a vital component in any Integrated Circuit (IC) system. Its complexity, due to its feedback and closed-loop nature, makes it an ideal example for demonstrating functional verification on a modeled analog DUT.