Comparative study of threshold voltage extraction methods for 55 nm CMOS technology at liquid helium temperature

Accurate determination of threshold voltage ($V_{\text{th}}$) is critical for MOSFET characterization and modeling, especially for emerging applications in cryogenic electronics, such as quantum computing and advanced scientific instrumentation. This paper presents a systematic comparative evaluation of multiple threshold voltage extraction methods applied to a commercial 55 nm bulk CMOS technology at liquid helium temperature ($\sim$4 K). We examine and adapt conventional extraction techniques—including Constant Current (CC), Linear Extrapolation (LE), Y-function (Yfunc), Transconductance Linear Extrapolation (GMLE), Second Derivative (SD), Third Derivative (TD), Transition-based (TM, NMID, NRH), and Transconductance-to-Current Ratio (TCR)-based methods—and assess their performance in terms of consistency, robustness against measurement noise, and applicability at cryogenic temperatures. Results indicate significant method-dependent variability in extracted threshold values at 4 K, reflecting fundamental differences in how each method handles cryogenic-specific effects such as dopant freeze-out and mobility variations. Through careful comparative analysis, we identify the most reliable and accurate extraction methods for low-temperature conditions, specifically SD, LE, TM, TD, GMLE, fitLE (fitted linear extrapolation), and Y-function, offering practical recommendations to improve device modeling accuracy and reliability for cryogenic CMOS circuits.