{"title":"DoS攻击下参数不匹配的弹性事件触发类同步控制。","authors":"Dong Xu, Yajuan Liu, Sangmoon Lee, Xiangpeng Xie","doi":"10.1016/j.isatra.2025.09.027","DOIUrl":null,"url":null,"abstract":"<p><p>This paper investigates quasi-synchronization of chaotic Lur'e systems (CLSs) with parameter mismatches under denial-of-service (DoS) attacks. A resilient memory event-triggered scheme (RMETS) is proposed to mitigate network congestion and attack-induced disruptions. Unlike conventional schemes requiring prior knowledge of attack timing, RMETS employs an acknowledgment (ACK) mechanism to detect packet loss and introduces an ACK-related performance loss term for adaptive adjustment of release probability. Historical release data are further incorporated to refine control updates at critical sampling instants, balancing communication demands with control performance. A co-design of RMETS and a memory-based controller ensures the quasi-synchronization of CLSs within a predefined error bound. The effectiveness of the proposed approach is validated through simulations using Chua's circuit.</p>","PeriodicalId":94059,"journal":{"name":"ISA transactions","volume":" ","pages":""},"PeriodicalIF":6.5000,"publicationDate":"2025-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Resilient event-triggered quasi-synchronization control for CLSs with parameter mismatches under DoS attacks.\",\"authors\":\"Dong Xu, Yajuan Liu, Sangmoon Lee, Xiangpeng Xie\",\"doi\":\"10.1016/j.isatra.2025.09.027\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p><p>This paper investigates quasi-synchronization of chaotic Lur'e systems (CLSs) with parameter mismatches under denial-of-service (DoS) attacks. A resilient memory event-triggered scheme (RMETS) is proposed to mitigate network congestion and attack-induced disruptions. Unlike conventional schemes requiring prior knowledge of attack timing, RMETS employs an acknowledgment (ACK) mechanism to detect packet loss and introduces an ACK-related performance loss term for adaptive adjustment of release probability. Historical release data are further incorporated to refine control updates at critical sampling instants, balancing communication demands with control performance. A co-design of RMETS and a memory-based controller ensures the quasi-synchronization of CLSs within a predefined error bound. The effectiveness of the proposed approach is validated through simulations using Chua's circuit.</p>\",\"PeriodicalId\":94059,\"journal\":{\"name\":\"ISA transactions\",\"volume\":\" \",\"pages\":\"\"},\"PeriodicalIF\":6.5000,\"publicationDate\":\"2025-09-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ISA transactions\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1016/j.isatra.2025.09.027\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISA transactions","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1016/j.isatra.2025.09.027","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Resilient event-triggered quasi-synchronization control for CLSs with parameter mismatches under DoS attacks.
This paper investigates quasi-synchronization of chaotic Lur'e systems (CLSs) with parameter mismatches under denial-of-service (DoS) attacks. A resilient memory event-triggered scheme (RMETS) is proposed to mitigate network congestion and attack-induced disruptions. Unlike conventional schemes requiring prior knowledge of attack timing, RMETS employs an acknowledgment (ACK) mechanism to detect packet loss and introduces an ACK-related performance loss term for adaptive adjustment of release probability. Historical release data are further incorporated to refine control updates at critical sampling instants, balancing communication demands with control performance. A co-design of RMETS and a memory-based controller ensures the quasi-synchronization of CLSs within a predefined error bound. The effectiveness of the proposed approach is validated through simulations using Chua's circuit.