{"title":"基于finfet的铁电存储器件的低压极化开关，利用电场非线性","authors":"Shreyam Natani, P. R. Bandaru","doi":"10.1007/s10825-025-02341-2","DOIUrl":null,"url":null,"abstract":"<div><p>Characteristics inherent to nonplanar geometries, with an aim to reduce program/erase voltages in ferroelectric field-effect transistor (FE-FET)-based memory devices, are proposed. The basis is the enhancement of the electric field in the FE films integrated with Fin-based FE-FETs (FE-FinFET), compared to FE films in planar FE-FETs. A new design (DE/FE-FinFET), based on combining FE and dielectric (DE) materials in the gate stack of FinFETs, is also proposed. Modeling and technology computer-aided design simulations indicate larger memory window at lower voltages in Fin-based FE-FETs. It is found that with nonplanar geometries a memory window can be observed at voltages 11% lower with FE-FinFETs and 33% lower with DE/FE-FinFETs compared to planar configurations.</p></div>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":"24 3","pages":""},"PeriodicalIF":2.5000,"publicationDate":"2025-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Low-voltage polarization switching in ferroelectric FinFET-based memory devices, using electric field nonlinearities\",\"authors\":\"Shreyam Natani, P. R. Bandaru\",\"doi\":\"10.1007/s10825-025-02341-2\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>Characteristics inherent to nonplanar geometries, with an aim to reduce program/erase voltages in ferroelectric field-effect transistor (FE-FET)-based memory devices, are proposed. The basis is the enhancement of the electric field in the FE films integrated with Fin-based FE-FETs (FE-FinFET), compared to FE films in planar FE-FETs. A new design (DE/FE-FinFET), based on combining FE and dielectric (DE) materials in the gate stack of FinFETs, is also proposed. Modeling and technology computer-aided design simulations indicate larger memory window at lower voltages in Fin-based FE-FETs. It is found that with nonplanar geometries a memory window can be observed at voltages 11% lower with FE-FinFETs and 33% lower with DE/FE-FinFETs compared to planar configurations.</p></div>\",\"PeriodicalId\":620,\"journal\":{\"name\":\"Journal of Computational Electronics\",\"volume\":\"24 3\",\"pages\":\"\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2025-05-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Computational Electronics\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://link.springer.com/article/10.1007/s10825-025-02341-2\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Computational Electronics","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10825-025-02341-2","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Low-voltage polarization switching in ferroelectric FinFET-based memory devices, using electric field nonlinearities
Characteristics inherent to nonplanar geometries, with an aim to reduce program/erase voltages in ferroelectric field-effect transistor (FE-FET)-based memory devices, are proposed. The basis is the enhancement of the electric field in the FE films integrated with Fin-based FE-FETs (FE-FinFET), compared to FE films in planar FE-FETs. A new design (DE/FE-FinFET), based on combining FE and dielectric (DE) materials in the gate stack of FinFETs, is also proposed. Modeling and technology computer-aided design simulations indicate larger memory window at lower voltages in Fin-based FE-FETs. It is found that with nonplanar geometries a memory window can be observed at voltages 11% lower with FE-FinFETs and 33% lower with DE/FE-FinFETs compared to planar configurations.
期刊介绍：
he Journal of Computational Electronics brings together research on all aspects of modeling and simulation of modern electronics. This includes optical, electronic, mechanical, and quantum mechanical aspects, as well as research on the underlying mathematical algorithms and computational details. The related areas of energy conversion/storage and of molecular and biological systems, in which the thrust is on the charge transport, electronic, mechanical, and optical properties, are also covered.
In particular, we encourage manuscripts dealing with device simulation; with optical and optoelectronic systems and photonics; with energy storage (e.g. batteries, fuel cells) and harvesting (e.g. photovoltaic), with simulation of circuits, VLSI layout, logic and architecture (based on, for example, CMOS devices, quantum-cellular automata, QBITs, or single-electron transistors); with electromagnetic simulations (such as microwave electronics and components); or with molecular and biological systems. However, in all these cases, the submitted manuscripts should explicitly address the electronic properties of the relevant systems, materials, or devices and/or present novel contributions to the physical models, computational strategies, or numerical algorithms.
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