Constrained Bayesian optimization using a Lagrange multiplier applied to power transistor design

We propose a novel constrained Bayesian optimization (BO) algorithm optimizing the design process of laterally-diffused metal-oxide-semiconductor (LDMOS) transistors while realizing a target breakdown voltage (\({{\varvec{BV}}}\)). We convert the constrained BO problem into a conventional BO problem using a Lagrange multiplier. Instead of directly optimizing the traditional Figure-of-Merit (FOM), we set the Lagrangian as the objective function of BO. This adaptive objective function with a changeable Lagrange multiplier can address constrained BO problems which have constraints that require costly evaluations, without the need for additional surrogate models to approximate constraints. Our algorithm enables a device designer to set the target \({{\varvec{BV}}}\) in the design space, and obtain a device that satisfies the optimized FOM and the target \({{\varvec{BV}}}\) constraint automatically. Utilizing this algorithm, we explore the physical limits of the FOM for our devices in the 30 – 50 V range within the defined design space.