Optimization of performance parameters of differential ring oscillator using Taguchi DoE and Pareto ANOVA techniques for fast-setting PLL frequency synthesizer

This paper presents the optimization of a differential ring oscillator (DRO) with dual control voltage using the Taguchi design of experiments (DoE) method and Pareto ANOVA for statistical performance analysis. A 3-stage DRO is designed, focusing on three key MOSFET width parameters (W_in, W_c1, W_c2), identified as critical to circuit behavior. Taguchi and ANOVA, performed using Minitab, determine the significance and optimal values of these parameters. Circuit simulations using SCL 180 nm CMOS technology and Cadence Virtuoso confirm the analytical predictions. The optimized DRO achieves a wide tuning range of 95.22% (0.5–10.44 GHz), low phase noise of–108.65 dBc/Hz at 1 MHz offset, and power consumption of 5.74 mW. A PLL frequency synthesizer is designed using this DRO, achieving a fast lock time of 0.4 \(\mu\)s, low jitter (5 ps), minimal reference spur, compact area (0.027 \(\text {mm}^{2}\)), and total power consumption of 9.45 mW at 1.8 V power supply. A new figure-of-merit (FoM) is also proposed. The synthesizer is suitable for applications in 5G, radar, satellite communications, MRI, GNSS, automotive systems, defense, and wireless power transfer.