Low-power computing with reversible logic: a modular approach to Vedic multiplication

Driven by the growing imperative for energy-efficient computing, reversible logic gates have gained significant attention for their ability to reduce energy dissipation. These gates are essential in advanced domains such as quantum computing, DNA computing, nanotechnology, and energy-aware CMOS design. This study presents an optimized 4 × 4-bit complex Vedic multiplier designed using reversible logic, alongside modular implementations of a 4 × 4-bit Vedic multiplier, unified 8-bit adder–subtractor and two variants of a 4-bit carry-save adder. The proposed architectures are evaluated based on key performance metrics, including ancilla inputs, garbage outputs, quantum cost, and gate count. Furthermore, an entropy-based validation grounded in Shannon’s information theory confirms logical reversibility of the circuits, reinforcing their potential for ultra-low-power and quantum computing applications.