Performance Evaluation of Junctionless Double Surrounding Gate Si Nanotube MOSFET Using Triple and Quadruple Metal Gate Work Function Engineering for the Upcoming Sub 2 nm Technology Node

In this work, Triple Metal (TM) and Quadruple Metal (QM) gate engineering have been done for both junctionless (JL) inversion mode (IM) and Double surrounding Gate (DSG) Si nanotube (SiNT) MOSFET to study drain current (I_D) characteristics for gate length of 2 nm using Silvaco ATLAS 3D TCAD. For this, the Non Equilibrium Green’s Function (NEGF) method has been used along with self-consistent solution of Schrödinger’s equation with Poisson’s equation. In case of IM channel region of SiNT device, there is lightly doping. In this device SiO₂ is used as gate oxide thickness of 0.8 nm, with Si channel radius of 1.5 nm have been used. A comparison has also been done between results of TM DSG and QM DSG SiNT. For a reasonable comparison between JL and IM SiNT, in each case of TM and QM JL SiNT doping concentration are optimized for two goals (i) to obtain the same I_ON as IM SiNT and (ii) to obtain the same threshold voltage (V_TH) as IM SiNT. This results in about 10 times smaller I_OFF for both JL, I_ON and V_TH matching SiNT for both TM and QM case. This also results in about 10 times higher I_ON/I_OFF current ratio for all JL device as compared to IM device for both TM and QM case. All used JL SiNT results in smaller DIBL in both TM and QM case as compared to IM SiNT device. In this work for JL SiNT, a smaller DIBL ~ 36.46 mV/V, nearly ideal subthreshold slope (SS) ~ 60 mV/dec, and higher I_ON/I_OFF current ratio ~ 4.41 × 10¹⁰ have been obtained in comparison to available literature CGAA device results.