{"title":"用于硬件加速器的5T-2MTJ stt辅助自旋-轨道-转矩三元内容可寻址存储器","authors":"Siri Narla;Piyush Kumar;Azad Naeemi","doi":"10.1109/TMAG.2025.3601525","DOIUrl":null,"url":null,"abstract":"In this work, we present a novel non-volatile spin transfer torque (STT)-assisted spin–orbit torque (SOT)-based ternary content addressable memory (TCAM) with five transistors and two magnetic tunnel junctions (MTJs). We perform a comprehensive study of the proposed design from the device level to the application level. At the device level, various write characteristics such as the write error rate, time, and current have been obtained using micromagnetic simulations. The array-level search and write performance have been evaluated based on SPICE circuit simulations with layout extracted parasitics for bit-cells while also accounting for the impact of interconnect parasitics at the 7 nm technology node. A search error rate (SER) of <inline-formula> <tex-math>$3.9 \\times 10 {^{-}11 }$ </tex-math></inline-formula> is projected for exact search while accounting for various sources of variation in the design. In addition, the resolution of the search operation is quantified under various scenarios to understand the achievable quality of the approximate search operations. Application-level performance and accuracy of the proposed design have been evaluated and benchmarked against other state-of-the-art CAM designs in the context of a CAM-based recommendation system.","PeriodicalId":13405,"journal":{"name":"IEEE Transactions on Magnetics","volume":"61 10","pages":"1-9"},"PeriodicalIF":1.9000,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 5T-2MTJ STT-Assisted Spin-Orbit-Torque-Based Ternary Content Addressable Memory for Hardware Accelerators\",\"authors\":\"Siri Narla;Piyush Kumar;Azad Naeemi\",\"doi\":\"10.1109/TMAG.2025.3601525\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, we present a novel non-volatile spin transfer torque (STT)-assisted spin–orbit torque (SOT)-based ternary content addressable memory (TCAM) with five transistors and two magnetic tunnel junctions (MTJs). We perform a comprehensive study of the proposed design from the device level to the application level. At the device level, various write characteristics such as the write error rate, time, and current have been obtained using micromagnetic simulations. The array-level search and write performance have been evaluated based on SPICE circuit simulations with layout extracted parasitics for bit-cells while also accounting for the impact of interconnect parasitics at the 7 nm technology node. A search error rate (SER) of <inline-formula> <tex-math>$3.9 \\\\times 10 {^{-}11 }$ </tex-math></inline-formula> is projected for exact search while accounting for various sources of variation in the design. In addition, the resolution of the search operation is quantified under various scenarios to understand the achievable quality of the approximate search operations. Application-level performance and accuracy of the proposed design have been evaluated and benchmarked against other state-of-the-art CAM designs in the context of a CAM-based recommendation system.\",\"PeriodicalId\":13405,\"journal\":{\"name\":\"IEEE Transactions on Magnetics\",\"volume\":\"61 10\",\"pages\":\"1-9\"},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2025-08-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Magnetics\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11134128/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Magnetics","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11134128/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A 5T-2MTJ STT-Assisted Spin-Orbit-Torque-Based Ternary Content Addressable Memory for Hardware Accelerators
In this work, we present a novel non-volatile spin transfer torque (STT)-assisted spin–orbit torque (SOT)-based ternary content addressable memory (TCAM) with five transistors and two magnetic tunnel junctions (MTJs). We perform a comprehensive study of the proposed design from the device level to the application level. At the device level, various write characteristics such as the write error rate, time, and current have been obtained using micromagnetic simulations. The array-level search and write performance have been evaluated based on SPICE circuit simulations with layout extracted parasitics for bit-cells while also accounting for the impact of interconnect parasitics at the 7 nm technology node. A search error rate (SER) of $3.9 \times 10 {^{-}11 }$ is projected for exact search while accounting for various sources of variation in the design. In addition, the resolution of the search operation is quantified under various scenarios to understand the achievable quality of the approximate search operations. Application-level performance and accuracy of the proposed design have been evaluated and benchmarked against other state-of-the-art CAM designs in the context of a CAM-based recommendation system.
期刊介绍:
Science and technology related to the basic physics and engineering of magnetism, magnetic materials, applied magnetics, magnetic devices, and magnetic data storage. The IEEE Transactions on Magnetics publishes scholarly articles of archival value as well as tutorial expositions and critical reviews of classical subjects and topics of current interest.