一种用于硅光子学中PWM热光调谐的状态切换数字LDO

IF 4.9 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Ziying Xie;Tianchi Ye;Ziyue Dang;Xi Xiao;Min Tan
{"title":"一种用于硅光子学中PWM热光调谐的状态切换数字LDO","authors":"Ziying Xie;Tianchi Ye;Ziyue Dang;Xi Xiao;Min Tan","doi":"10.1109/TCSII.2025.3598759","DOIUrl":null,"url":null,"abstract":"Pulse-width-modulated (PWM) thermo-optic tuning in silicon photonics calls for a power supply featuring high-speed PWM power output with short settling time, high efficiency, and a compact size. However, the transient response of the traditional digital low-dropout regulators (DLDOs) is limited by the closed-loop response, which makes it difficult to meet the speed requirements of the PWM power output. This brief presents a State-Switching DLDO (SS-DLDO), specially optimized for PWM thermo-optic tuning. Two state selectors, controlled by a PWM signal, are inserted into the SS-DLDO structure to control the connections and operational states of the DLDO asynchronously. This enables the speed of PWM tuning to be decoupled from the feedback loop of the DLDO. The proposed design is fabricated in a 65nm CMOS process with an active area of 0.00634 mm2. Measurement results show that the rising-edge settling time and falling-edge settling time of the PWM power output are 16.3 ns and 14 ns, respectively, which effectively reduces the limit of the edge settling time to the achievable PWM duty cycle range. Under a 2 MHz PWM frequency, this design can achieve PWM duty cycles ranging from 5.92% to 97.2%, corresponding to output power ranging from 1.47 mW to 24.12 mW.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 10","pages":"1458-1462"},"PeriodicalIF":4.9000,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A State-Switching Digital LDO for PWM Thermo-Optic Tuning in Silicon Photonics\",\"authors\":\"Ziying Xie;Tianchi Ye;Ziyue Dang;Xi Xiao;Min Tan\",\"doi\":\"10.1109/TCSII.2025.3598759\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Pulse-width-modulated (PWM) thermo-optic tuning in silicon photonics calls for a power supply featuring high-speed PWM power output with short settling time, high efficiency, and a compact size. However, the transient response of the traditional digital low-dropout regulators (DLDOs) is limited by the closed-loop response, which makes it difficult to meet the speed requirements of the PWM power output. This brief presents a State-Switching DLDO (SS-DLDO), specially optimized for PWM thermo-optic tuning. Two state selectors, controlled by a PWM signal, are inserted into the SS-DLDO structure to control the connections and operational states of the DLDO asynchronously. This enables the speed of PWM tuning to be decoupled from the feedback loop of the DLDO. The proposed design is fabricated in a 65nm CMOS process with an active area of 0.00634 mm2. Measurement results show that the rising-edge settling time and falling-edge settling time of the PWM power output are 16.3 ns and 14 ns, respectively, which effectively reduces the limit of the edge settling time to the achievable PWM duty cycle range. Under a 2 MHz PWM frequency, this design can achieve PWM duty cycles ranging from 5.92% to 97.2%, corresponding to output power ranging from 1.47 mW to 24.12 mW.\",\"PeriodicalId\":13101,\"journal\":{\"name\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"volume\":\"72 10\",\"pages\":\"1458-1462\"},\"PeriodicalIF\":4.9000,\"publicationDate\":\"2025-08-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Circuits and Systems II: Express Briefs\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11124547/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11124547/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

摘要

硅光子学中的脉宽调制(PWM)热光调谐需要一种具有高速PWM功率输出、稳定时间短、效率高、体积小的电源。然而,传统数字低压差稳压器(dldo)的瞬态响应受到闭环响应的限制,难以满足PWM功率输出的速度要求。本文介绍了一种状态切换DLDO (SS-DLDO),专门针对PWM热光调谐进行了优化。在SS-DLDO结构中插入两个由PWM信号控制的状态选择器,以异步控制DLDO的连接和工作状态。这使得PWM调谐的速度与DLDO的反馈回路解耦。该设计采用65nm CMOS工艺,有效面积为0.00634 mm2。测量结果表明,PWM功率输出的上升沿稳定时间和下降沿稳定时间分别为16.3 ns和14 ns,有效地降低了边缘稳定时间对PWM占空比范围的限制。在2 MHz的PWM频率下,本设计可以实现5.92% ~ 97.2%的PWM占空比,对应的输出功率范围为1.47 mW ~ 24.12 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A State-Switching Digital LDO for PWM Thermo-Optic Tuning in Silicon Photonics
Pulse-width-modulated (PWM) thermo-optic tuning in silicon photonics calls for a power supply featuring high-speed PWM power output with short settling time, high efficiency, and a compact size. However, the transient response of the traditional digital low-dropout regulators (DLDOs) is limited by the closed-loop response, which makes it difficult to meet the speed requirements of the PWM power output. This brief presents a State-Switching DLDO (SS-DLDO), specially optimized for PWM thermo-optic tuning. Two state selectors, controlled by a PWM signal, are inserted into the SS-DLDO structure to control the connections and operational states of the DLDO asynchronously. This enables the speed of PWM tuning to be decoupled from the feedback loop of the DLDO. The proposed design is fabricated in a 65nm CMOS process with an active area of 0.00634 mm2. Measurement results show that the rising-edge settling time and falling-edge settling time of the PWM power output are 16.3 ns and 14 ns, respectively, which effectively reduces the limit of the edge settling time to the achievable PWM duty cycle range. Under a 2 MHz PWM frequency, this design can achieve PWM duty cycles ranging from 5.92% to 97.2%, corresponding to output power ranging from 1.47 mW to 24.12 mW.
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来源期刊
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Circuits and Systems II: Express Briefs 工程技术-工程:电子与电气
CiteScore
7.90
自引率
20.50%
发文量
883
审稿时长
3.0 months
期刊介绍: TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes: Circuits: Analog, Digital and Mixed Signal Circuits and Systems Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic Circuits and Systems, Power Electronics and Systems Software for Analog-and-Logic Circuits and Systems Control aspects of Circuits and Systems.
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