Sub-threshold 10 T FinFET-based single-ended SRAM cell for energy-efficient high-speed operation

An ultra-low-power, high-speed 10-transistor (P10T) sub-threshold Static Random-Access Memory (SRAM) bit-cell featuring single-ended operation has been proposed and evaluated in this work. To enhance read stability and minimize read delay, a decoupled read path comprising an inverter and a low threshold voltage transistor has been employed. Furthermore, writability and write delay have been improved by integrating a power gating mechanism in the write path. The bit-cell design also benefits from reduced leakage power, which is attributed to the elimination of bitline leakage during read operations and the stacked transistors availability in the SRAM core. The bit-cell has been designed using 18 nm FinFET technology and analyzed under both near-threshold (near-Vt) and super-threshold (super-Vt) operating conditions. Comparative assessments were performed against several state-of-the-art single-ended 10 T and 11 T SRAM cells, as well as the traditional 6 T SRAM architecture. In the near-Vt region, the proposed design has demonstrated lower leakage power by 40.44 %, 25.07 %, 29.87 %, 0.58 %, 46.35 %, and 10.41 % when compared to 6 T, ESE10T, HSLP10T, ULP10T, FC11T, and LPWE11T designs, respectively. Additionally, improvements in read and write delays have been observed, with reductions of 3.61x/1.08x, 3.59x/2.51x, 3.82x/1.32x, 5.44x/1.57x, and 3.80x/1.08x relative to the same respective cells in the near-Vt region. The proposed cell area has been measured as 2.924 µm², which is approximately 1.794 times more than that of a conventional 6 T cell. To provide a more comprehensive evaluation, an Electrical Quality Metric (EQM) was formulated, incorporating all key performance indicators. Using this metric, the proposed SRAM bit-cell demonstrated enhanced performance in both near-threshold (near-Vt) and above-threshold (super-Vt) operating modes relative to the other evaluated designs.