Mobility Enhancement in Monolayer MoS2 Transistors on a Polyimide Substrate by Reducing Localized Charge Trap Effect

Monolayer molybdenum disulfide (MoS₂) is a promising candidate for flexible electronics, but its electron mobility on polymer substrates is typically constrained to below 10 cm² V^–1 s^–1. To investigate this limitation, we fabricate top-gated monolayer MoS₂ field-effect transistor (FET) on a polyimide substrate with a SiO_x seed (SiO_x FET). Our electron transport model reveals that the localized charge trapping (LCT) effect is the primary mobility-limiting mechanism. The sources of LCT, structural defects in the monolayer MoS₂ and interfacial defects from the SiO_x seed layer, are systematically suppressed via a transfer optimization (TO) process and a vacuum annealing (VA) strategy, respectively. By combining TO with an optimized-VA strategy, the SiO_x FET (TO+VA) achieves a high mobility of 24.8 cm² V^–1 s^–1, demonstrating a significant mobility enhancement at low and high electron densities, compared to the untreated SiO_x FET. Crucially, the dominant mobility-limiting mechanism shifts from the LCT effect in the untreated SiO_x FET to Coulomb impurity scattering in the SiO_x FET (TO+VA). The fundamental study underscores a model-guided approach to systematically mitigate the LCT effect, enabling high-mobility monolayer MoS₂ devices on polymer substrates.