先进的无线胎儿监测系统,采用STBC,早期FECG预测和高效的加密硬件

IF 1.4 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
S. Navaneethan, Arti Ranjan, M. Amutha, Usha Bala Varanasi, C. R. Bharathi
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引用次数: 0

摘要

本文提出了一种用于胎儿监测系统的高性能无线架构,该架构集成了时空块编码(STBC)、新型双吞吐量多重累积(DTMAC)和早期胎儿心电图(FECG)预测单元,以解决数据可靠性、安全性和处理效率方面的挑战。STBC通过利用空间和时间分集增强了衰落环境下的通信鲁棒性,而基于lms的自适应波束形成改善了信号接收,并实现了FECG信号的动态早期预测。采用轻量级Naïve贝叶斯分类器对胎儿信号进行分类,准确率较高。为了保证数据传输的安全性,本文提出了一种基于线性反馈移位寄存器(LFSRs)的低开销AES加密方案。DTMAC单元设计了基于Ladner-Fisher的双精度累加器,显著加快了乘法累加运算。该体系结构在Verilog HDL中建模,并使用Xilinx Vivado进行合成。对现有方法的评估显示了改进的性能,查找表(LUT)使用量减少到543,门数减少到4,692,内存使用量减少到164,422 KB。功耗降低到156.70 mW,延迟减少22.4%,吞吐量增加18.6%。使用MIT PhysioNet的实时脑电图数据集进行验证。这些结果突出了所提出的系统在提供安全、准确和实时的无线胎儿监测方面的效率,使其成为下一代医疗保健应用的有前途的解决方案。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Advanced wireless fetal monitoring system using STBC, early FECG prediction, and high-efficiency encryption hardware

Advanced wireless fetal monitoring system using STBC, early FECG prediction, and high-efficiency encryption hardware

This paper presents a high-performance wireless architecture for fetal monitoring systems, integrating Space Time Block Coding (STBC), novel Double Throughput Multiple Accumulate (DTMAC), and early Fetal Electrocardiogram (FECG) prediction unit to address challenges in data reliability, security, and processing efficiency. STBC enhances communication robustness in fading environments by leveraging spatial and temporal diversity, while LMS-based adaptive beamforming improves signal reception and enables dynamic early prediction of FECG signals. A lightweight Naïve Bayes classifier is employed to classify fetal signals with high accuracy. For secure data transmission, a low-overhead AES encryption scheme using Linear Feedback Shift Registers (LFSRs) is implemented. The DTMAC unit, designed with a Ladner-Fisher based double-precision accumulate adder, significantly accelerates multiply-accumulate operations. The architecture was modeled in Verilog HDL and synthesized using Xilinx Vivado. Evaluation against existing methods demonstrates improved performance, with lookup table (LUT) usage reduced to 543, gate count minimized to 4,692, and memory usage decreased to 164,422 KB. Power consumption was lowered to 156.70 mW, with a 22.4% reduction in latency and an 18.6% increase in throughput. Validation was conducted using real-time FECG datasets from MIT PhysioNet. These results highlight the proposed system's efficiency in delivering secure, accurate, and real-time wireless fetal monitoring, making it a promising solution for next-generation healthcare applications.

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来源期刊
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing 工程技术-工程:电子与电气
CiteScore
0.30
自引率
7.10%
发文量
141
审稿时长
7.3 months
期刊介绍: Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today. A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.
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