A delay-constrained optimization framework for low-power VLSI interconnect design using mathematical signal models

As VLSI technology scales to sub-7 nm nodes, interconnect-related delay and power dissipation become dominant design bottlenecks. This paper presents a comprehensive mathematical framework for modeling and optimizing interconnects in very-large-scale integration (VLSI) systems under delay constraints. Leveraging signal processing theory and circuit-level modeling, we introduce an enhanced delay model incorporating Elmore delay, crosstalk effects, and capacitive coupling. A constrained optimization strategy using Lagrangian relaxation and Karush–Kuhn–Tucker conditions is applied to minimize dynamic power while preserving signal integrity. Simulation results on 7 nm process technology demonstrate that the proposed method achieves up to 23% reduction in power with marginal delay overheads. Our framework is validated using HSPICE and Cadence Spectre on standard ISCAS85 and OpenCore benchmarks, providing a practical path to energy-efficient interconnect design.