Design of a Multichannel, 14-bit, 3-MS/s Hybrid ADC Based on SAR-TDC Two-Stage Conversion for Dark Matter Particle Detection

The precision charge measurement of a gamma ray radiation detector consisting of scintillation crystals coupled with photomultiplier tubes (PMTs) is critical in the dark matter particle detection application. A high-resolution high-speed analog-to-digital converter (ADC) is required to digitize the amplitude of the generated pulse signals from the front-end readout electronics. In this article, we propose a novel hybrid ADC based on two-stage conversion to achieve high resolution and high sampling rate, and the key design technique of this ADC lies in optimizing the combination of successive approximation register (SAR) and time-to-digital converter (TDC) accuracy through system-level performance evaluation, ultimately achieving a high energy-efficiency ratio. A 14-bit hybrid ADC, which is composed of a 5-bit SAR, a 4-bit coarse TDC, and a 5-bit fine TDC, is proposed. A 16-channel prototype chip is designed in a 180-nm CMOS process with a 1.8/3.3 V power supply voltage. The die size is $2850\times 3350~\mu \text {m}$ . A sampling rate of 3 MS/s is achieved at the clock frequency of 100 MHz, and the power consumption is 1.6 mW per channel. With the digital calibration, the proposed ADC achieves the differential nonlinearity (DNL) of +0.67/-0.58 LSB, the integral nonlinearity (INL) of +2.3/-0.91 LSB, the spurious free dynamic range (SFDR) of 81.59 dB, the effective number of bits (ENOB) of 11.22 bits, and the Figure of Merit (FoM) of 223.58 fJ/conv per channel.