高效、可靠、安全的PUF架构,具有温度不变性和ML攻击弹性

IF 2.5 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Nitish Kumar , Aakif Nehal , Aditya Vikram Singh , Kavindra Kandpal , Manish Goswami
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引用次数: 0

摘要

物理不可克隆功能(puf)为安全认证和密钥生成提供了先进的硬件解决方案。他们利用半导体制造过程中产生的固有的、不可预测的和不可避免的差异。这些特定于每个芯片的独特特性被利用在PUF电路中,为设备产生独特且不可克隆的标识符。通过利用现代半导体工艺中存在的这些随机变化,puf加强了硬件和软件的安全性,提供了一种可靠有效的方法来保护数字系统免受潜在威胁。在本文中,使用高效电路设计的电流缺乏,老化弹性逆变器和线性反馈移位寄存器(LFSR)导致可靠性从80.06%增加到98.06%。在-40°C到120°C的宽温度范围内,实现的独特性、均匀性和位混化分别为49.21%、50.08%和50.08%,功耗比传统的Arbiter PUF低约1.57倍。仿真结果表明,布局前和布局后的延迟分别为1.08 ns和1.95 ns。NIST的测试还显示,所提出的设计在响应中具有随机性。所提出的设计也在Xilinx Vivado上进行了实验验证,并在Digilent Basys 3 Artix-7 FPGA上实现,硬件资源最少,比特生成速率为95 Mb/秒。此外,所提出的设计显示出对机器学习(ML)攻击的弹性,对PUF响应的预测精度约为55%至79.3%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Efficient, reliable, and secure PUF architecture with temperature invariance and ML attack resilience
Physically Unclonable Functions (PUFs) provide an advanced hardware solution for secure authentication and key generation. They utilize the inherent, unpredictable, and unavoidable differences created during semiconductor manufacturing. These unique characteristics, specific to each chip, are harnessed in PUF circuits to produce distinct and unclonable identifiers for devices. By taking advantage of these random variations present in modern semiconductor processes, PUFs strengthen both hardware and software security, offering a dependable and effective way to protect digital systems from potential threats. In this proposed paper, the use of efficient circuit design for Current starved, aging resilient inverter, and linear feedback shift register (LFSR) have resulted in the increase of reliability from 80.06% to 98.06%. The uniqueness, uniformity, and bit-aliasing achieved are of 49.21%, 50.08% and 50.08% , respectively, for a wide temperature range spanning from -40°C to 120°C and reduction of power dissipation to approximately 1.57 times less than the conventional Arbiter PUF. The pre-layout and post-layout Simulation results showed a delay of 1.08 ns and 1.95 ns respectively. The NIST test also revealed that the proposed design had randomness in the response. The proposed designs are also experimentally verified using Xilinx Vivado and implemented on Digilent Basys 3 Artix-7 FPGA, with minimum hardware resources, with a bit generation rate of 95 Mb/sec. Additionally, the proposed design exhibits resilience against machine learning (ML) attacks, with a prediction accuracy of approximately 55% to 79.3% for the PUF responses.
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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