{"title":"高效、可靠、安全的PUF架构,具有温度不变性和ML攻击弹性","authors":"Nitish Kumar , Aakif Nehal , Aditya Vikram Singh , Kavindra Kandpal , Manish Goswami","doi":"10.1016/j.vlsi.2025.102538","DOIUrl":null,"url":null,"abstract":"<div><div>Physically Unclonable Functions (PUFs) provide an advanced hardware solution for secure authentication and key generation. They utilize the inherent, unpredictable, and unavoidable differences created during semiconductor manufacturing. These unique characteristics, specific to each chip, are harnessed in PUF circuits to produce distinct and unclonable identifiers for devices. By taking advantage of these random variations present in modern semiconductor processes, PUFs strengthen both hardware and software security, offering a dependable and effective way to protect digital systems from potential threats. In this proposed paper, the use of efficient circuit design for Current starved, aging resilient inverter, and linear feedback shift register (LFSR) have resulted in the increase of reliability from 80.06% to 98.06%. The uniqueness, uniformity, and bit-aliasing achieved are of 49.21%, 50.08% and 50.08% , respectively, for a wide temperature range spanning from -40°C to 120°C and reduction of power dissipation to approximately 1.57 times less than the conventional Arbiter PUF. The pre-layout and post-layout Simulation results showed a delay of 1.08 ns and 1.95 ns respectively. The NIST test also revealed that the proposed design had randomness in the response. The proposed designs are also experimentally verified using Xilinx Vivado and implemented on Digilent Basys 3 Artix-7 FPGA, with minimum hardware resources, with a bit generation rate of 95 Mb/sec. Additionally, the proposed design exhibits resilience against machine learning (ML) attacks, with a prediction accuracy of approximately 55% to 79.3% for the PUF responses.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102538"},"PeriodicalIF":2.5000,"publicationDate":"2025-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Efficient, reliable, and secure PUF architecture with temperature invariance and ML attack resilience\",\"authors\":\"Nitish Kumar , Aakif Nehal , Aditya Vikram Singh , Kavindra Kandpal , Manish Goswami\",\"doi\":\"10.1016/j.vlsi.2025.102538\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>Physically Unclonable Functions (PUFs) provide an advanced hardware solution for secure authentication and key generation. They utilize the inherent, unpredictable, and unavoidable differences created during semiconductor manufacturing. These unique characteristics, specific to each chip, are harnessed in PUF circuits to produce distinct and unclonable identifiers for devices. By taking advantage of these random variations present in modern semiconductor processes, PUFs strengthen both hardware and software security, offering a dependable and effective way to protect digital systems from potential threats. In this proposed paper, the use of efficient circuit design for Current starved, aging resilient inverter, and linear feedback shift register (LFSR) have resulted in the increase of reliability from 80.06% to 98.06%. The uniqueness, uniformity, and bit-aliasing achieved are of 49.21%, 50.08% and 50.08% , respectively, for a wide temperature range spanning from -40°C to 120°C and reduction of power dissipation to approximately 1.57 times less than the conventional Arbiter PUF. The pre-layout and post-layout Simulation results showed a delay of 1.08 ns and 1.95 ns respectively. The NIST test also revealed that the proposed design had randomness in the response. The proposed designs are also experimentally verified using Xilinx Vivado and implemented on Digilent Basys 3 Artix-7 FPGA, with minimum hardware resources, with a bit generation rate of 95 Mb/sec. Additionally, the proposed design exhibits resilience against machine learning (ML) attacks, with a prediction accuracy of approximately 55% to 79.3% for the PUF responses.</div></div>\",\"PeriodicalId\":54973,\"journal\":{\"name\":\"Integration-The Vlsi Journal\",\"volume\":\"106 \",\"pages\":\"Article 102538\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2025-09-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Integration-The Vlsi Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167926025001956\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025001956","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Efficient, reliable, and secure PUF architecture with temperature invariance and ML attack resilience
Physically Unclonable Functions (PUFs) provide an advanced hardware solution for secure authentication and key generation. They utilize the inherent, unpredictable, and unavoidable differences created during semiconductor manufacturing. These unique characteristics, specific to each chip, are harnessed in PUF circuits to produce distinct and unclonable identifiers for devices. By taking advantage of these random variations present in modern semiconductor processes, PUFs strengthen both hardware and software security, offering a dependable and effective way to protect digital systems from potential threats. In this proposed paper, the use of efficient circuit design for Current starved, aging resilient inverter, and linear feedback shift register (LFSR) have resulted in the increase of reliability from 80.06% to 98.06%. The uniqueness, uniformity, and bit-aliasing achieved are of 49.21%, 50.08% and 50.08% , respectively, for a wide temperature range spanning from -40°C to 120°C and reduction of power dissipation to approximately 1.57 times less than the conventional Arbiter PUF. The pre-layout and post-layout Simulation results showed a delay of 1.08 ns and 1.95 ns respectively. The NIST test also revealed that the proposed design had randomness in the response. The proposed designs are also experimentally verified using Xilinx Vivado and implemented on Digilent Basys 3 Artix-7 FPGA, with minimum hardware resources, with a bit generation rate of 95 Mb/sec. Additionally, the proposed design exhibits resilience against machine learning (ML) attacks, with a prediction accuracy of approximately 55% to 79.3% for the PUF responses.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.