Vertically stacked GAA–SOI FinFET-based CFETs for low-power and RF applications: DC, QSCV, and AC performance analysis

In this work, a novel Complementary Field-Effect Transistor (CFET) is proposed, featuring a vertically stacked configuration of an n-type Silicon-on-Insulator FinFET (SOI-FinFET) and a p-type Gate-All-Around (GAA) Nanosheet transistor with a shared gate. The proposed device is analyzed using the Silvaco TCAD tool to evaluate key performance metrics, such as ON current (Ion), OFF current (Ioff), threshold voltage (Vth), subthreshold swing (SS), gain, cut-off frequency, and quasi-static capacitance-voltage (C–V) characteristics. A critical aspect of this study is the introduction of an oxide layer between the SOI-FinFET (nMOS) and GAA (pMOS) transistors, which effectively minimizes parasitic capacitance and enhances overall performance. Simulation results show that the proposed CFET structure achieves superior SS, increased Ion, and reduced Ioff, along with excellent scalability compared to conventional counterparts. These advantages render the novel ultra-short channel CFET highly suitable for high-performance, low-power electronic applications. The proposed structure is anticipated to improve the performance of future sub-nanometer devices, potentially replacing traditional CMOS technology.