用2位加法器实现图像处理中的不精确乘法器

IF 2.5 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Parthibaraj Anguraj , Thiruvenkadam Krishnan
{"title":"用2位加法器实现图像处理中的不精确乘法器","authors":"Parthibaraj Anguraj ,&nbsp;Thiruvenkadam Krishnan","doi":"10.1016/j.vlsi.2025.102510","DOIUrl":null,"url":null,"abstract":"<div><div>The inexact multiplier architecture represents a foundational element of approximate computing, serving a critical function across diverse error-tolerant applications. This paper delves into the complexities of three distinct inexact multiplier designs, each meticulously optimized for image processing applications. This work introduces a strategic partitioning of the partial product stage into smaller segments, subsequently implementing decoder algorithms, truncation methods, exact 2-bit adder and proposed multiplexer-based imprecise 2-bit adder circuits. These resulting 8<span><math><mo>×</mo></math></span> 8 imprecise multipliers exhibit advantageous error metrics and streamlined design complexity. When benchmarked against traditional inexact multipliers, these architectures achieve notable reductions in both area and power consumption, as validated by modeling conducted via the Cadence RTL compiler with TSMC’s 90 nm technology. The proposed approximation model demonstrates substantial area and power reductions of 37.19% and 46.14%, respectively, compared to precise multipliers, all while sustaining acceptable error metrics. Additionally, the developed 8<span><math><mo>×</mo></math></span> 8 multipliers surpass other approximate multiplier architectures in performance metrics, making them particularly effective for image multiplication and sharpening.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"106 ","pages":"Article 102510"},"PeriodicalIF":2.5000,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Implementation of imprecise multipliers using 2-bit adder for image processing\",\"authors\":\"Parthibaraj Anguraj ,&nbsp;Thiruvenkadam Krishnan\",\"doi\":\"10.1016/j.vlsi.2025.102510\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>The inexact multiplier architecture represents a foundational element of approximate computing, serving a critical function across diverse error-tolerant applications. This paper delves into the complexities of three distinct inexact multiplier designs, each meticulously optimized for image processing applications. This work introduces a strategic partitioning of the partial product stage into smaller segments, subsequently implementing decoder algorithms, truncation methods, exact 2-bit adder and proposed multiplexer-based imprecise 2-bit adder circuits. These resulting 8<span><math><mo>×</mo></math></span> 8 imprecise multipliers exhibit advantageous error metrics and streamlined design complexity. When benchmarked against traditional inexact multipliers, these architectures achieve notable reductions in both area and power consumption, as validated by modeling conducted via the Cadence RTL compiler with TSMC’s 90 nm technology. The proposed approximation model demonstrates substantial area and power reductions of 37.19% and 46.14%, respectively, compared to precise multipliers, all while sustaining acceptable error metrics. Additionally, the developed 8<span><math><mo>×</mo></math></span> 8 multipliers surpass other approximate multiplier architectures in performance metrics, making them particularly effective for image multiplication and sharpening.</div></div>\",\"PeriodicalId\":54973,\"journal\":{\"name\":\"Integration-The Vlsi Journal\",\"volume\":\"106 \",\"pages\":\"Article 102510\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2025-09-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Integration-The Vlsi Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167926025001671\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025001671","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

摘要

不精确乘法器架构代表了近似计算的基本元素,在各种容错应用程序中发挥关键作用。本文深入研究了三种不同的不精确乘法器设计的复杂性,每种乘法器都针对图像处理应用进行了精心优化。本工作介绍了将部分乘积阶段战略性地划分为更小的部分,随后实现了解码器算法、截断方法、精确2位加法器和基于多路复用器的非精确2位加法器电路。由此产生的8× 8不精确乘法器显示出有利的误差度量和简化的设计复杂性。当与传统的不精确乘数器进行基准测试时,这些架构在面积和功耗方面都显着降低,正如通过采用台积电90nm技术的Cadence RTL编译器进行的建模所验证的那样。与精确乘法器相比,该近似模型的面积和功耗分别减少了37.19%和46.14%,同时保持了可接受的误差指标。此外,开发的8x8乘法器在性能指标上优于其他近似乘法器架构,使其在图像乘法和锐化方面特别有效。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Implementation of imprecise multipliers using 2-bit adder for image processing
The inexact multiplier architecture represents a foundational element of approximate computing, serving a critical function across diverse error-tolerant applications. This paper delves into the complexities of three distinct inexact multiplier designs, each meticulously optimized for image processing applications. This work introduces a strategic partitioning of the partial product stage into smaller segments, subsequently implementing decoder algorithms, truncation methods, exact 2-bit adder and proposed multiplexer-based imprecise 2-bit adder circuits. These resulting 8× 8 imprecise multipliers exhibit advantageous error metrics and streamlined design complexity. When benchmarked against traditional inexact multipliers, these architectures achieve notable reductions in both area and power consumption, as validated by modeling conducted via the Cadence RTL compiler with TSMC’s 90 nm technology. The proposed approximation model demonstrates substantial area and power reductions of 37.19% and 46.14%, respectively, compared to precise multipliers, all while sustaining acceptable error metrics. Additionally, the developed 8× 8 multipliers surpass other approximate multiplier architectures in performance metrics, making them particularly effective for image multiplication and sharpening.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信