{"title":"具有介电袋和堆叠氧化物结构的垂直纳米线场效应管的DC/RF性能分析","authors":"Rajat Gulghane , Archana Pandey , Swaroop Kumar Macherla , Kavicharan Mummaneni , Ekta Goel","doi":"10.1016/j.micrna.2025.208337","DOIUrl":null,"url":null,"abstract":"<div><div>As transistors shrink, the gate oxide must become extremely thin. This leads to a quantum mechanical effect called direct tunneling. This creates a significant gate leakage current which is a major source of power consumption and heat in modern chips. Instead of a single thin layer of Silicon Dioxide (SiO<sub>2</sub>), a stacked oxide and dielectric pocket are used for stronger control of the channel. Hence, this manuscript presents an analysis of a Vertical Nanowire FET device featuring a stacked oxide and dielectric pocket configuration. It demonstrates that the device exhibits improved performance characteristics compared to previously reported data. In this work, the proposed device has been evaluated concerning conventional VNWFET and Dielectric Pocket VNWFET (DP-VNWFET). The device's DC analysis has been conducted, analyzing DC performance metrics such as I<sub>ON</sub>, I<sub>OFF</sub>, I<sub>ON</sub>/I<sub>OFF</sub> ratio, subthreshold swing (SS), and threshold voltage (V<sub>t</sub>) in comparison to existing reported work. Furthermore, the AC/RF performance of the device has been evaluated based on performance metrics such as transconductance (g<sub>m</sub>), output transconductance (g<sub>d</sub>), intrinsic gain, gain-bandwidth product (GBP), cutoff frequency, and transconductance frequency product (TFP). The proposed device exhibits excellent characteristics and proves to be highly suitable for both current and emerging technological advancements.</div></div>","PeriodicalId":100923,"journal":{"name":"Micro and Nanostructures","volume":"208 ","pages":"Article 208337"},"PeriodicalIF":3.0000,"publicationDate":"2025-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"DC/RF performance analysis of vertical Nnanowire FET with dielectric pocket and stacked oxide configuration\",\"authors\":\"Rajat Gulghane , Archana Pandey , Swaroop Kumar Macherla , Kavicharan Mummaneni , Ekta Goel\",\"doi\":\"10.1016/j.micrna.2025.208337\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>As transistors shrink, the gate oxide must become extremely thin. This leads to a quantum mechanical effect called direct tunneling. This creates a significant gate leakage current which is a major source of power consumption and heat in modern chips. Instead of a single thin layer of Silicon Dioxide (SiO<sub>2</sub>), a stacked oxide and dielectric pocket are used for stronger control of the channel. Hence, this manuscript presents an analysis of a Vertical Nanowire FET device featuring a stacked oxide and dielectric pocket configuration. It demonstrates that the device exhibits improved performance characteristics compared to previously reported data. In this work, the proposed device has been evaluated concerning conventional VNWFET and Dielectric Pocket VNWFET (DP-VNWFET). The device's DC analysis has been conducted, analyzing DC performance metrics such as I<sub>ON</sub>, I<sub>OFF</sub>, I<sub>ON</sub>/I<sub>OFF</sub> ratio, subthreshold swing (SS), and threshold voltage (V<sub>t</sub>) in comparison to existing reported work. Furthermore, the AC/RF performance of the device has been evaluated based on performance metrics such as transconductance (g<sub>m</sub>), output transconductance (g<sub>d</sub>), intrinsic gain, gain-bandwidth product (GBP), cutoff frequency, and transconductance frequency product (TFP). The proposed device exhibits excellent characteristics and proves to be highly suitable for both current and emerging technological advancements.</div></div>\",\"PeriodicalId\":100923,\"journal\":{\"name\":\"Micro and Nanostructures\",\"volume\":\"208 \",\"pages\":\"Article 208337\"},\"PeriodicalIF\":3.0000,\"publicationDate\":\"2025-09-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Micro and Nanostructures\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S2773012325002663\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"PHYSICS, CONDENSED MATTER\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Micro and Nanostructures","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2773012325002663","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"PHYSICS, CONDENSED MATTER","Score":null,"Total":0}
DC/RF performance analysis of vertical Nnanowire FET with dielectric pocket and stacked oxide configuration
As transistors shrink, the gate oxide must become extremely thin. This leads to a quantum mechanical effect called direct tunneling. This creates a significant gate leakage current which is a major source of power consumption and heat in modern chips. Instead of a single thin layer of Silicon Dioxide (SiO2), a stacked oxide and dielectric pocket are used for stronger control of the channel. Hence, this manuscript presents an analysis of a Vertical Nanowire FET device featuring a stacked oxide and dielectric pocket configuration. It demonstrates that the device exhibits improved performance characteristics compared to previously reported data. In this work, the proposed device has been evaluated concerning conventional VNWFET and Dielectric Pocket VNWFET (DP-VNWFET). The device's DC analysis has been conducted, analyzing DC performance metrics such as ION, IOFF, ION/IOFF ratio, subthreshold swing (SS), and threshold voltage (Vt) in comparison to existing reported work. Furthermore, the AC/RF performance of the device has been evaluated based on performance metrics such as transconductance (gm), output transconductance (gd), intrinsic gain, gain-bandwidth product (GBP), cutoff frequency, and transconductance frequency product (TFP). The proposed device exhibits excellent characteristics and proves to be highly suitable for both current and emerging technological advancements.