Aaron D. Pitcher;Charl W. Baard;Mihail S. Georgiev;Natalia K. Nikolova
{"title":"准确的高速等效时间采样接收器:架构和性能指标","authors":"Aaron D. Pitcher;Charl W. Baard;Mihail S. Georgiev;Natalia K. Nikolova","doi":"10.1109/TIM.2025.3604952","DOIUrl":null,"url":null,"abstract":"An equivalent-time (ET) sampling ultra-wideband (UWB) dual-channel receiver is proposed, which is controlled by a field-programmable gate array (FPGA). It has a programmable repetition period and ET sampling rate [up to 20 gigasamples per second (GSa/s)]. The architecture employs a programmable delay chip (PDC) to achieve ultra-high speed of over 8900 traces/s for a typical <inline-formula> <tex-math>$1~\\mu $ </tex-math></inline-formula>s repetition period. Compared with previously reported high-speed (PDC-based) receivers, it offers superior time-sampling accuracy. The design incorporates a custom dual-channel radio frequency (RF) front end with a low-jitter clock source, critical in achieving time-sampling stability. Importantly, a simple yet effective method is proposed to correct the systematic timebase distortions due to the PDC, whose delay inaccuracies are the main signal-degradation factor in ET receivers realizing picosecond sampling intervals. The realized low-cost system operates as a high-speed oscilloscope with a 10-dB receiver bandwidth of 6 GHz and with accuracy comparable to that of bench-top high-speed oscilloscopes. Performance metrics and measurement procedures are proposed to evaluate and compare time-sampling receivers. These are applied to the proposed receiver, including tests as part of a compact pulsed radar. Its performance is compared with two high-speed bench-top oscilloscopes as well as previously reported ET receiver prototypes.","PeriodicalId":13341,"journal":{"name":"IEEE Transactions on Instrumentation and Measurement","volume":"74 ","pages":"1-15"},"PeriodicalIF":5.9000,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11147170","citationCount":"0","resultStr":"{\"title\":\"Accurate High-Speed Equivalent-Time Sampling Receiver: Architecture and Performance Metrics\",\"authors\":\"Aaron D. Pitcher;Charl W. Baard;Mihail S. Georgiev;Natalia K. Nikolova\",\"doi\":\"10.1109/TIM.2025.3604952\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An equivalent-time (ET) sampling ultra-wideband (UWB) dual-channel receiver is proposed, which is controlled by a field-programmable gate array (FPGA). It has a programmable repetition period and ET sampling rate [up to 20 gigasamples per second (GSa/s)]. The architecture employs a programmable delay chip (PDC) to achieve ultra-high speed of over 8900 traces/s for a typical <inline-formula> <tex-math>$1~\\\\mu $ </tex-math></inline-formula>s repetition period. Compared with previously reported high-speed (PDC-based) receivers, it offers superior time-sampling accuracy. The design incorporates a custom dual-channel radio frequency (RF) front end with a low-jitter clock source, critical in achieving time-sampling stability. Importantly, a simple yet effective method is proposed to correct the systematic timebase distortions due to the PDC, whose delay inaccuracies are the main signal-degradation factor in ET receivers realizing picosecond sampling intervals. The realized low-cost system operates as a high-speed oscilloscope with a 10-dB receiver bandwidth of 6 GHz and with accuracy comparable to that of bench-top high-speed oscilloscopes. Performance metrics and measurement procedures are proposed to evaluate and compare time-sampling receivers. These are applied to the proposed receiver, including tests as part of a compact pulsed radar. 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Accurate High-Speed Equivalent-Time Sampling Receiver: Architecture and Performance Metrics
An equivalent-time (ET) sampling ultra-wideband (UWB) dual-channel receiver is proposed, which is controlled by a field-programmable gate array (FPGA). It has a programmable repetition period and ET sampling rate [up to 20 gigasamples per second (GSa/s)]. The architecture employs a programmable delay chip (PDC) to achieve ultra-high speed of over 8900 traces/s for a typical $1~\mu $ s repetition period. Compared with previously reported high-speed (PDC-based) receivers, it offers superior time-sampling accuracy. The design incorporates a custom dual-channel radio frequency (RF) front end with a low-jitter clock source, critical in achieving time-sampling stability. Importantly, a simple yet effective method is proposed to correct the systematic timebase distortions due to the PDC, whose delay inaccuracies are the main signal-degradation factor in ET receivers realizing picosecond sampling intervals. The realized low-cost system operates as a high-speed oscilloscope with a 10-dB receiver bandwidth of 6 GHz and with accuracy comparable to that of bench-top high-speed oscilloscopes. Performance metrics and measurement procedures are proposed to evaluate and compare time-sampling receivers. These are applied to the proposed receiver, including tests as part of a compact pulsed radar. Its performance is compared with two high-speed bench-top oscilloscopes as well as previously reported ET receiver prototypes.
期刊介绍:
Papers are sought that address innovative solutions to the development and use of electrical and electronic instruments and equipment to measure, monitor and/or record physical phenomena for the purpose of advancing measurement science, methods, functionality and applications. The scope of these papers may encompass: (1) theory, methodology, and practice of measurement; (2) design, development and evaluation of instrumentation and measurement systems and components used in generating, acquiring, conditioning and processing signals; (3) analysis, representation, display, and preservation of the information obtained from a set of measurements; and (4) scientific and technical support to establishment and maintenance of technical standards in the field of Instrumentation and Measurement.