Investigating the effects of interface trap charges and temperature on n-type step tunneling path TFET

This work presents the design and analysis of a Step Tunneling Path (STP) TFET, aimed at enhancing tunneling control and making it suitable for low power applications. The device performance is evaluated under varying interface trap charge (ITC) densities ranging from 10¹² cm⁻² to 3 × 10¹² cm⁻² and temperature conditions from 300 K to 500 K. The DC analysis investigates the influence of positive and negative ITCs on transfer characteristics, energy band diagram shifts at ambipolar states, BTBT rate, and threshold voltage. Additionally, the effects of ITC concentration on AC parameters such as gate capacitance, transconductance, and cut-off frequency are examined. The study also includes a comprehensive evaluation of DC and RF/analog performance over the specified temperature range. The findings provide valuable insights into optimizing STP TFET performance and reliability for low-power electronic applications.