On estimating the threshold voltage of vertical junctionless GaN power fin-MOSFETs

Traditional analytical models derived for Si logic devices fail to estimate the threshold voltage (V_TH) of vertical junctionless GaN power Fin-channel metal oxide semiconductor field effect transistors (VJ GaN Fin-MOSFETs). Solving two-dimensional Poisson’s equation inside the drift region of VJ GaN Fin- MOSFETs is not a viable option as of now. Thus, we report an alternate methodology to derive the analytical model for estimating the V_TH of VJ GaN Fin-MOSFETs. The proposed model uses an available baseline model followed by adding tuning parameters to the baseline model via a standard procedure. The proposed model faithfully predicts the effect of crucial geometrical and bias parameters on V_TH; along with estimating the drain induced barrier lowering effect. The proposed methodology is generic in nature; it can be applied to other (ultra)wide bandgap semiconductor based VJ power MOSFETs that are currently under extensive investigation.