基于数据加权平均的25 kHz-BW 98.6 db信噪比多比特Delta-Sigma调制器

IF 3 4区计算机科学 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Chinese Journal of Electronics Pub Date : 2025-07-01 DOI:10.23919/cje.2024.00.131

Xinpeng Xing;Jing Xue;Gaofeng Luan;Haigang Feng

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引用次数: 0

摘要

本文提出了一种用于音频应用的高精度Delta-Sigma调制器（DSM）。该调制器由带反馈的积分器级联实现，具有三阶噪声整形和4位量化，保证了调制器的稳定性，将过采样比限制在64，大大简化了积分器放大器的设计。采用一阶数据加权平均技术抑制多位电容式数模转换器因单元失配引起的谐波失真。采用0.18 μm互补金属氧化物半导体（CMOS）工艺制作的DSM测试芯片，在25 kHz带宽（BW）下，信噪比（SNR）为98.6 dB，信噪加失真比为91.5 dB。调制器从3.3 V电源消耗12.38 mW功率，对应于154.6 dB的竞争参数值。

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A 25 kHz-BW 98.6 dB-SNR Multi-Bit Delta-Sigma Modulator with Data-Weighted Averaging

This paper presents a high-precision Delta-Sigma Modulator (DSM) for audio applications. The modulator is implemented by cascade of integrators with feedback with 3rd-order noise shaping and 4-bit quantization, guaranteeing the modulator stability, limiting the oversampling ratio to 64, and greatly relaxing the integrator amplifier design. First-order data-weighted averaging technique is included to suppress harmonic distortion introduced by cell mismatch of multi-bit capacitive digital-to-analog converter. Fabricated in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process, the DSM test chip achieves a signal-to-noise ratio (SNR) of 98.6 dB, a signal-to-noise-plus-distortion ratio of 91.5 dB for 25 kHz bandwidth (BW). The modulator consumes 12.38 mW power from 3.3 V supplies, corresponding to a competitive figure-of-merit of 154.6 dB.

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来源期刊

Chinese Journal of Electronics 工程技术-工程：电子与电气

CiteScore

3.70

自引率

16.70%

发文量

342

审稿时长

12.0 months

期刊介绍： CJE focuses on the emerging fields of electronics, publishing innovative and transformative research papers. Most of the papers published in CJE are from universities and research institutes, presenting their innovative research results. Both theoretical and practical contributions are encouraged, and original research papers reporting novel solutions to the hot topics in electronics are strongly recommended.