一种生物医学应用的基于模拟relu的决策树电路结构

IF 1.4 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Vassilis Alimisis, Vasileios Moustakas, Konstantinos Cheliotis, Anna Mylona, Paul P. Sotiriadis
{"title":"一种生物医学应用的基于模拟relu的决策树电路结构","authors":"Vassilis Alimisis,&nbsp;Vasileios Moustakas,&nbsp;Konstantinos Cheliotis,&nbsp;Anna Mylona,&nbsp;Paul P. Sotiriadis","doi":"10.1007/s10470-025-02481-2","DOIUrl":null,"url":null,"abstract":"<div><p>This paper presents a low-power and high performance decision tree classifier for biomedical applications. The proposed architecture consists of Current Comparator circuits, ReLu circuits, Gaussian function circuits, analog multipliers, Current Mirrors and argmax operator. All the circuits operate in the sub-threshold region in order to achieve power-efficiency. The principles of the architecture are thoroughly described and realized in an energy-efficient set-up that consumes less than 956 nW and operates on low supply rails of 0.6 V. When tested on real-world biomedical classification tasks, the proposed design achieved a classification accuracy exceeding <span>\\(91.30\\%\\)</span>. The Cadence IC Suite was used for the schematic design and layout, and the implementation was carried out using 90 nm CMOS technology. The robustness of the classifier was evaluated through corner-case analysis and Monte Carlo simulations, accounting for process variations and mismatches. The accuracy and reliable performance of the proposed architecture were confirmed by comparing post-layout simulation results with those of a software-based classifier and relevant prior studies.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"125 1","pages":""},"PeriodicalIF":1.4000,"publicationDate":"2025-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-025-02481-2.pdf","citationCount":"0","resultStr":"{\"title\":\"An analog ReLu-based decision tree circuit architecture for biomedical applications\",\"authors\":\"Vassilis Alimisis,&nbsp;Vasileios Moustakas,&nbsp;Konstantinos Cheliotis,&nbsp;Anna Mylona,&nbsp;Paul P. Sotiriadis\",\"doi\":\"10.1007/s10470-025-02481-2\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>This paper presents a low-power and high performance decision tree classifier for biomedical applications. The proposed architecture consists of Current Comparator circuits, ReLu circuits, Gaussian function circuits, analog multipliers, Current Mirrors and argmax operator. All the circuits operate in the sub-threshold region in order to achieve power-efficiency. The principles of the architecture are thoroughly described and realized in an energy-efficient set-up that consumes less than 956 nW and operates on low supply rails of 0.6 V. When tested on real-world biomedical classification tasks, the proposed design achieved a classification accuracy exceeding <span>\\\\(91.30\\\\%\\\\)</span>. The Cadence IC Suite was used for the schematic design and layout, and the implementation was carried out using 90 nm CMOS technology. The robustness of the classifier was evaluated through corner-case analysis and Monte Carlo simulations, accounting for process variations and mismatches. The accuracy and reliable performance of the proposed architecture were confirmed by comparing post-layout simulation results with those of a software-based classifier and relevant prior studies.</p></div>\",\"PeriodicalId\":7827,\"journal\":{\"name\":\"Analog Integrated Circuits and Signal Processing\",\"volume\":\"125 1\",\"pages\":\"\"},\"PeriodicalIF\":1.4000,\"publicationDate\":\"2025-08-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://link.springer.com/content/pdf/10.1007/s10470-025-02481-2.pdf\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Analog Integrated Circuits and Signal Processing\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://link.springer.com/article/10.1007/s10470-025-02481-2\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analog Integrated Circuits and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10470-025-02481-2","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

摘要

提出了一种低功耗、高性能的生物医学决策树分类器。该架构由电流比较器电路、ReLu电路、高斯函数电路、模拟乘法器、电流镜和argmax算子组成。所有电路都在亚阈值区域工作,以实现功率效率。该架构的原理得到了全面的描述,并在能耗低于956 nW的节能设置中实现,并在0.6 V的低电源轨道上运行。当在现实世界的生物医学分类任务中进行测试时,所提出的设计实现了超过\(91.30\%\)的分类精度。采用Cadence IC Suite进行原理图设计和布局,采用90nm CMOS技术实现。通过拐角案例分析和蒙特卡罗模拟来评估分类器的鲁棒性,考虑到过程变化和不匹配。通过将布局后的仿真结果与基于软件的分类器和相关研究结果进行比较,验证了所提架构的准确性和可靠性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An analog ReLu-based decision tree circuit architecture for biomedical applications

This paper presents a low-power and high performance decision tree classifier for biomedical applications. The proposed architecture consists of Current Comparator circuits, ReLu circuits, Gaussian function circuits, analog multipliers, Current Mirrors and argmax operator. All the circuits operate in the sub-threshold region in order to achieve power-efficiency. The principles of the architecture are thoroughly described and realized in an energy-efficient set-up that consumes less than 956 nW and operates on low supply rails of 0.6 V. When tested on real-world biomedical classification tasks, the proposed design achieved a classification accuracy exceeding \(91.30\%\). The Cadence IC Suite was used for the schematic design and layout, and the implementation was carried out using 90 nm CMOS technology. The robustness of the classifier was evaluated through corner-case analysis and Monte Carlo simulations, accounting for process variations and mismatches. The accuracy and reliable performance of the proposed architecture were confirmed by comparing post-layout simulation results with those of a software-based classifier and relevant prior studies.

求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing 工程技术-工程:电子与电气
CiteScore
0.30
自引率
7.10%
发文量
141
审稿时长
7.3 months
期刊介绍: Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today. A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信