Hardware/Software Co-design for spike communication optimization: Leveraging neuron-level communication patterns

Neuromorphic hardware is specifically designed to accelerate Spiking Neural Network (SNN) computations through multiple computing cores interconnected via network-on-chip (NoC) infrastructure. However, spike communication has emerged as a significant bottleneck, limiting the overall performance of neuromorphic systems. By analyzing the communication characteristics of SNNs, we identify two dominant neuron-level communication patterns: spatially consistent local communication and many-to-same communication. To address these challenges, we present a co-optimization framework comprising (1) at the software level, we leverage the spatially consistent local communication to introduce a novel cross-layer topological sorting algorithm, which improves the initial SNN placement, followed by a lightweight fine-tuning algorithm to further optimize the placement, and (2) at the hardware level, inspired by the many-to-same communication, we introduce a novel spike event merge routing mechanism that consolidates multiple spike events into unified packets, effectively reducing NoC traffic density through packet aggregation. Comprehensive evaluation across six SNN benchmarks demonstrates significant improvements in communication latency and energy consumption.