BCH译码器的节能症候群计算架构

IF 3.1 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-07-10 DOI:10.1109/TVLSI.2025.3585971

Jeongmin Kim;Jaehoon Kwon;Hansol Jeong;In-Cheol Park

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引用次数: 0

摘要

症候群计算（SC）是BCH译码的关键步骤，其计算效率直接影响整个译码器的能耗。本文提出了一种针对BCH解码器的节能SC架构。所提出的架构从根本上采用了基于剩余的SC，它比传统的霍纳基于方法的SC消耗更少的能量。此外，与以前基于余数的方法不同，它使用最小多项式来产生更短的余数，从而减少了计算量并提高了能源效率。实施结果表明，与最新的Horner基于方法的SC单元相比，能效提高了80%，与之前的基于剩余的SC单元相比，能效提高了35%。

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Energy-Efficient Syndrome Calculation Architecture for BCH Decoders

Syndrome calculation (SC) is a critical step in Bose-Chaudhuri-Hocquenghem (BCH) decoding, and its computational efficiency significantly impacts the energy consumption of the entire decoder. This article proposes an energy-efficient SC architecture designed for BCH decoders. The proposed architecture fundamentally adopts a remainder-based SC, which consumes less energy than the conventional Horner’s method-based SC unit. Furthermore, unlike previous remainder-based approaches, it uses a minimal polynomial to produce a shorter remainder, leading to reduced computation and improved energy efficiency. Implementation results demonstrate an 80% improvement in energy efficiency compared to the latest Horner’s method-based SC unit and a 35% improvement compared to the previous remainder-based SC unit.

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.