{"title":"WF-SPR:一种加权单扇出方法用于基于概率的信号可靠性估计","authors":"Yue Xiang, Zhen Wang","doi":"10.1016/j.vlsi.2025.102507","DOIUrl":null,"url":null,"abstract":"<div><div>With continuous improvement of circuit integration, the circuit fault rate has increased. Consequently, accurately and efficiently analyzing and predicting circuit reliability has become a critical objective in digital integrated circuit design. In recent years, as approximate computing circuits (AACs) are getting closer to practical applications, evaluating their reliability has become particularly important. Whether in conventional circuits or AACs, the signal correlation problem caused by fanout nodes can affect the accuracy of circuit reliability evaluation. Moreover, precise reliability evaluation algorithms often come with high computational costs. In this paper, we propose a reliability evaluation method for conventional circuits considering the weight of single fanout nodes based on the signal probability reliability (SPR) method. Meanwhile, this paper improves the method and proposes a new reliability analysis method for AACs. Experimental results on circuits in the ISCAS85 and EvoApprox8b library show that the proposed method has good accuracy and scalability. On both conventional circuits and AACs, the two proposed methods achieve an average error rate of 1% with a time overhead of 0.1% compared to the Monte Carlo (MC) method. On conventional circuits, the average error rate is reduced by 76% compared to the SPR method, and the time overhead is reduced by 97% compared to the SPR multi-pass (SPR-MP) method.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102507"},"PeriodicalIF":2.5000,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"WF-SPR: A weighted single fanout approach for signal probability-based reliability estimation\",\"authors\":\"Yue Xiang, Zhen Wang\",\"doi\":\"10.1016/j.vlsi.2025.102507\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>With continuous improvement of circuit integration, the circuit fault rate has increased. Consequently, accurately and efficiently analyzing and predicting circuit reliability has become a critical objective in digital integrated circuit design. In recent years, as approximate computing circuits (AACs) are getting closer to practical applications, evaluating their reliability has become particularly important. Whether in conventional circuits or AACs, the signal correlation problem caused by fanout nodes can affect the accuracy of circuit reliability evaluation. Moreover, precise reliability evaluation algorithms often come with high computational costs. In this paper, we propose a reliability evaluation method for conventional circuits considering the weight of single fanout nodes based on the signal probability reliability (SPR) method. Meanwhile, this paper improves the method and proposes a new reliability analysis method for AACs. Experimental results on circuits in the ISCAS85 and EvoApprox8b library show that the proposed method has good accuracy and scalability. On both conventional circuits and AACs, the two proposed methods achieve an average error rate of 1% with a time overhead of 0.1% compared to the Monte Carlo (MC) method. On conventional circuits, the average error rate is reduced by 76% compared to the SPR method, and the time overhead is reduced by 97% compared to the SPR multi-pass (SPR-MP) method.</div></div>\",\"PeriodicalId\":54973,\"journal\":{\"name\":\"Integration-The Vlsi Journal\",\"volume\":\"105 \",\"pages\":\"Article 102507\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2025-08-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Integration-The Vlsi Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167926025001646\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025001646","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
WF-SPR: A weighted single fanout approach for signal probability-based reliability estimation
With continuous improvement of circuit integration, the circuit fault rate has increased. Consequently, accurately and efficiently analyzing and predicting circuit reliability has become a critical objective in digital integrated circuit design. In recent years, as approximate computing circuits (AACs) are getting closer to practical applications, evaluating their reliability has become particularly important. Whether in conventional circuits or AACs, the signal correlation problem caused by fanout nodes can affect the accuracy of circuit reliability evaluation. Moreover, precise reliability evaluation algorithms often come with high computational costs. In this paper, we propose a reliability evaluation method for conventional circuits considering the weight of single fanout nodes based on the signal probability reliability (SPR) method. Meanwhile, this paper improves the method and proposes a new reliability analysis method for AACs. Experimental results on circuits in the ISCAS85 and EvoApprox8b library show that the proposed method has good accuracy and scalability. On both conventional circuits and AACs, the two proposed methods achieve an average error rate of 1% with a time overhead of 0.1% compared to the Monte Carlo (MC) method. On conventional circuits, the average error rate is reduced by 76% compared to the SPR method, and the time overhead is reduced by 97% compared to the SPR multi-pass (SPR-MP) method.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.