{"title":"WEnSIBR:使用支持编码和区域磨损均衡的动态基进行压缩","authors":"Swati Upadhyay , Arijit Nath , Hemangee K. Kapoor","doi":"10.1016/j.sysarc.2025.103543","DOIUrl":null,"url":null,"abstract":"<div><div>Non-Volatile Memories (NVM) are potential candidates to replace DRAM in main memory with a few intrinsic flaws associated with their writes, like poor endurance, excessive energy consumption, and long latency. Bit-flips due to costly write activities degrade the memory lifetime. We proposed SIBR, which compresses the incoming cacheblocks before writing in memory. Compressed blocks lead to lesser write activities in the memory cells. For further bit-flip reduction, we propose an extension of SIBR called EnSIBR that performs encoding on the SIBR-generated compressed blocks with relatively low storage overhead. However, only a small portion of memory, corresponding to the compressed block, is involved in write activity, leading to skewed bit-flip reception by memory cells.</div><div>Our second contribution is an intra-line wear-leveling method, which makes logical partitions of the memory lines called zones. We use the concept of <em>age</em> of a zone, which indicates the number of writes the zone has incurred over time. We also consider the number of bit-flips experienced by the zones with each write. The proposal, WEnSIBR, evens out the skewed distribution created by SIBR and EnSIBR. The novelty of WEnSIBR lies in its ability to uniformly distribute and simultaneously reduce bit-flips, which boosts the NVM lifetime significantly.</div></div>","PeriodicalId":50027,"journal":{"name":"Journal of Systems Architecture","volume":"168 ","pages":"Article 103543"},"PeriodicalIF":4.1000,"publicationDate":"2025-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"WEnSIBR: Compression using dynamic bases supported with encoding and zone wise wear leveling for NVMs\",\"authors\":\"Swati Upadhyay , Arijit Nath , Hemangee K. Kapoor\",\"doi\":\"10.1016/j.sysarc.2025.103543\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>Non-Volatile Memories (NVM) are potential candidates to replace DRAM in main memory with a few intrinsic flaws associated with their writes, like poor endurance, excessive energy consumption, and long latency. Bit-flips due to costly write activities degrade the memory lifetime. We proposed SIBR, which compresses the incoming cacheblocks before writing in memory. Compressed blocks lead to lesser write activities in the memory cells. For further bit-flip reduction, we propose an extension of SIBR called EnSIBR that performs encoding on the SIBR-generated compressed blocks with relatively low storage overhead. However, only a small portion of memory, corresponding to the compressed block, is involved in write activity, leading to skewed bit-flip reception by memory cells.</div><div>Our second contribution is an intra-line wear-leveling method, which makes logical partitions of the memory lines called zones. We use the concept of <em>age</em> of a zone, which indicates the number of writes the zone has incurred over time. We also consider the number of bit-flips experienced by the zones with each write. The proposal, WEnSIBR, evens out the skewed distribution created by SIBR and EnSIBR. The novelty of WEnSIBR lies in its ability to uniformly distribute and simultaneously reduce bit-flips, which boosts the NVM lifetime significantly.</div></div>\",\"PeriodicalId\":50027,\"journal\":{\"name\":\"Journal of Systems Architecture\",\"volume\":\"168 \",\"pages\":\"Article 103543\"},\"PeriodicalIF\":4.1000,\"publicationDate\":\"2025-08-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Systems Architecture\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1383762125002152\",\"RegionNum\":2,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Systems Architecture","FirstCategoryId":"94","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1383762125002152","RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
WEnSIBR: Compression using dynamic bases supported with encoding and zone wise wear leveling for NVMs
Non-Volatile Memories (NVM) are potential candidates to replace DRAM in main memory with a few intrinsic flaws associated with their writes, like poor endurance, excessive energy consumption, and long latency. Bit-flips due to costly write activities degrade the memory lifetime. We proposed SIBR, which compresses the incoming cacheblocks before writing in memory. Compressed blocks lead to lesser write activities in the memory cells. For further bit-flip reduction, we propose an extension of SIBR called EnSIBR that performs encoding on the SIBR-generated compressed blocks with relatively low storage overhead. However, only a small portion of memory, corresponding to the compressed block, is involved in write activity, leading to skewed bit-flip reception by memory cells.
Our second contribution is an intra-line wear-leveling method, which makes logical partitions of the memory lines called zones. We use the concept of age of a zone, which indicates the number of writes the zone has incurred over time. We also consider the number of bit-flips experienced by the zones with each write. The proposal, WEnSIBR, evens out the skewed distribution created by SIBR and EnSIBR. The novelty of WEnSIBR lies in its ability to uniformly distribute and simultaneously reduce bit-flips, which boosts the NVM lifetime significantly.
期刊介绍:
The Journal of Systems Architecture: Embedded Software Design (JSA) is a journal covering all design and architectural aspects related to embedded systems and software. It ranges from the microarchitecture level via the system software level up to the application-specific architecture level. Aspects such as real-time systems, operating systems, FPGA programming, programming languages, communications (limited to analysis and the software stack), mobile systems, parallel and distributed architectures as well as additional subjects in the computer and system architecture area will fall within the scope of this journal. Technology will not be a main focus, but its use and relevance to particular designs will be. Case studies are welcome but must contribute more than just a design for a particular piece of software.
Design automation of such systems including methodologies, techniques and tools for their design as well as novel designs of software components fall within the scope of this journal. Novel applications that use embedded systems are also central in this journal. While hardware is not a part of this journal hardware/software co-design methods that consider interplay between software and hardware components with and emphasis on software are also relevant here.