{"title":"一种新型紧凑型无乘法器忆阻晶体管仿真器的设计及其在神经形态与混沌生成中的应用","authors":"Manoj Kumar , Shireesh Kumar Rai , Bhawna Aggarwal , Maneesha Gupta","doi":"10.1016/j.vlsi.2025.102511","DOIUrl":null,"url":null,"abstract":"<div><div>This paper presents a compact configuration of memtranstor (MT), a new memory element having direct relation between magnetic flux (φ) and charge (q). The proposed configuration offers a simple architecture as it is designed without the need of any multiplier or any other complex component. This emulator has been realized by employing one operational transconductance amplifier (OTA), one current differencing transconductance amplifier (CDTA), and one voltage differencing current conveyor (VDCC) along with a few passive components. The emulator captures the fundamental relationship between φ and q, enabling the realization of distinctive pinched hysteresis loops under sinusoidal excitation, a hallmark of memtranstive behavior. It is designed to operate at a supply voltage of ±1.25 V. The circuit offers tunability through the variation in biasing voltages ensuring flexibility for a wide range of applications. The accuracy and dynamic characteristics of the proposed architecture are verified through mathematical analysis and LTSpice simulations with a 180 nm CMOS model. To assess the behavior of the proposed emulator in real environment, process-voltage-temperature analysis has been carried out followed by the designing of full custom layout in an area of 4464.88 μm<sup>2</sup>. Furthermore, non-ideal analysis has been carried out considering the parasitic elements at various terminals of the blocks employed in the circuit design. Additionally, to prove the practical feasibility of the proposed circuit, its operation has been confirmed by macro-models of the designated ICs followed by the bread-board implementation using commercial ICs under ±12 V supply voltage. To demonstrate practical utility, the emulator is employed in two key applications: an artificial synapse for neuromorphic systems and a nonlinear chaotic oscillator, both showcasing its relevance for next-generation memory-driven analog computing. The proposed design stands out due to its low component count, compact design, and ease of integration, making it a promising candidate for emerging fields like neuromorphic engineering and chaos-based systems. Furthermore, it provides valuable insights for future research in MT-based nonlinear dynamics and holds significant potential for advancing MT driven applications in neuromorphic computing and beyond.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"105 ","pages":"Article 102511"},"PeriodicalIF":2.5000,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of a new compact multiplier-less memtranstor emulator and its application in neuromorphic and chaos generation\",\"authors\":\"Manoj Kumar , Shireesh Kumar Rai , Bhawna Aggarwal , Maneesha Gupta\",\"doi\":\"10.1016/j.vlsi.2025.102511\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>This paper presents a compact configuration of memtranstor (MT), a new memory element having direct relation between magnetic flux (φ) and charge (q). The proposed configuration offers a simple architecture as it is designed without the need of any multiplier or any other complex component. This emulator has been realized by employing one operational transconductance amplifier (OTA), one current differencing transconductance amplifier (CDTA), and one voltage differencing current conveyor (VDCC) along with a few passive components. The emulator captures the fundamental relationship between φ and q, enabling the realization of distinctive pinched hysteresis loops under sinusoidal excitation, a hallmark of memtranstive behavior. It is designed to operate at a supply voltage of ±1.25 V. The circuit offers tunability through the variation in biasing voltages ensuring flexibility for a wide range of applications. The accuracy and dynamic characteristics of the proposed architecture are verified through mathematical analysis and LTSpice simulations with a 180 nm CMOS model. To assess the behavior of the proposed emulator in real environment, process-voltage-temperature analysis has been carried out followed by the designing of full custom layout in an area of 4464.88 μm<sup>2</sup>. Furthermore, non-ideal analysis has been carried out considering the parasitic elements at various terminals of the blocks employed in the circuit design. Additionally, to prove the practical feasibility of the proposed circuit, its operation has been confirmed by macro-models of the designated ICs followed by the bread-board implementation using commercial ICs under ±12 V supply voltage. To demonstrate practical utility, the emulator is employed in two key applications: an artificial synapse for neuromorphic systems and a nonlinear chaotic oscillator, both showcasing its relevance for next-generation memory-driven analog computing. The proposed design stands out due to its low component count, compact design, and ease of integration, making it a promising candidate for emerging fields like neuromorphic engineering and chaos-based systems. Furthermore, it provides valuable insights for future research in MT-based nonlinear dynamics and holds significant potential for advancing MT driven applications in neuromorphic computing and beyond.</div></div>\",\"PeriodicalId\":54973,\"journal\":{\"name\":\"Integration-The Vlsi Journal\",\"volume\":\"105 \",\"pages\":\"Article 102511\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2025-08-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Integration-The Vlsi Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167926025001683\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025001683","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Design of a new compact multiplier-less memtranstor emulator and its application in neuromorphic and chaos generation
This paper presents a compact configuration of memtranstor (MT), a new memory element having direct relation between magnetic flux (φ) and charge (q). The proposed configuration offers a simple architecture as it is designed without the need of any multiplier or any other complex component. This emulator has been realized by employing one operational transconductance amplifier (OTA), one current differencing transconductance amplifier (CDTA), and one voltage differencing current conveyor (VDCC) along with a few passive components. The emulator captures the fundamental relationship between φ and q, enabling the realization of distinctive pinched hysteresis loops under sinusoidal excitation, a hallmark of memtranstive behavior. It is designed to operate at a supply voltage of ±1.25 V. The circuit offers tunability through the variation in biasing voltages ensuring flexibility for a wide range of applications. The accuracy and dynamic characteristics of the proposed architecture are verified through mathematical analysis and LTSpice simulations with a 180 nm CMOS model. To assess the behavior of the proposed emulator in real environment, process-voltage-temperature analysis has been carried out followed by the designing of full custom layout in an area of 4464.88 μm2. Furthermore, non-ideal analysis has been carried out considering the parasitic elements at various terminals of the blocks employed in the circuit design. Additionally, to prove the practical feasibility of the proposed circuit, its operation has been confirmed by macro-models of the designated ICs followed by the bread-board implementation using commercial ICs under ±12 V supply voltage. To demonstrate practical utility, the emulator is employed in two key applications: an artificial synapse for neuromorphic systems and a nonlinear chaotic oscillator, both showcasing its relevance for next-generation memory-driven analog computing. The proposed design stands out due to its low component count, compact design, and ease of integration, making it a promising candidate for emerging fields like neuromorphic engineering and chaos-based systems. Furthermore, it provides valuable insights for future research in MT-based nonlinear dynamics and holds significant potential for advancing MT driven applications in neuromorphic computing and beyond.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.