A 38-GHz Differential Transimpedance Amplifier With Unbalanced Neutralizing Technique

In this letter, a broadband, low-noise and low-mismatch differential transimpedance amplifier (TIA) is proposed. In the classical single-ended-to-differential (S2D) strategy of TIA for mismatch reduction, the strong path and the weak path compensate each other, which results in low mismatch output differential signals. However, due to the different input strength of the strong and weak signals but the same gains of amplifier’s differential branches, mismatches could not eliminate well. To address this problem, an unbalanced neutralizing technique (UNT) is proposed. A single-sided negative capacitance feedback capacitor is introduced to strengthen the weak-side signal. Additionally, the design employs a combination of the high-gain input-stage and gain peaking in the subsequent stage to achieve improved bandwidth and noise performance simultaneously. Fabricated by 28-nm CMOS process, the chip achieves a transimpedance (TI) gain of 66.4 dB $\Omega $ across a 3-dB bandwidth of 38.8 GHz. The power consumption is 49 mW (including buffer). The averaged input-referred current noise density is 16.3 pA/ $\sqrt {\mathrm {Hz}}$ . The total active area of the chip is 0.08 mm².