ESegNet-ILT: An end-to-end mask optimization method in VLSI design flow based on enhanced SegNet

With the advancement of technology, the critical dimensions of integrated circuits continue to shrink, leading to an increasing mismatch between the photolithography system and feature sizes. As a result, mask optimization has become a key challenge in the design process of very large-scale integrated circuits (VLSI). In recent years, resolution enhancement technology (RET) and inverse lithography technology (ILT) have been widely used in the field of optical proximity correction (OPC). However, when using inverse lithography technology (ILT) for mask optimization, there are still high computational costs, and the mask's printability is not ideal. To address these issues, this paper proposes ESegNet-ILT, an end-to-end learning-based OPC method. Built on an improved version of SegNet, this approach incorporates convolutional attention modules and multi-scale feature extraction modules, and then incorporates traditional ILT for fine-tuning and refinement to generate higher-quality masks. By introducing convolutional attention block and multi-scale feature extraction module. The model effectively integrates rich feature information across different scales and focuses more on the key features of the target layout, enabling it to generate better initial mask solutions. These initial solutions are then refined through ILT fine-tuning to produce mask with higher printability. Experimental results demonstrate that this method achieves better mask printability and robustness, while reducing bridging defects in printed image. Compared to the state-of-the-art methods, the proposed method reduces the process variation band (PVB) by 15 % while ensuring comparable squared L2 error, and accelerates the turnaround time (TAT) by 2.47 times.