基于sfq的近似计算体系结构建模与设备级指南

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2025-03-26 DOI:10.1109/LCA.2025.3573740

Pratiksha Mundhe;Yuta Hano;Satoshi Kawakami;Teruo Tanimoto;Masamitsu Tanaka;Koji Inoue;Ilkwon Byun

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引用次数: 0

摘要

单通量量子（SFQ）逻辑由于其超快和低能量的运行而成为一种有前途的后摩尔技术。然而，尽管在各个领域取得了进展，但由于冷却成本过高，其可行性受到质疑。经过验证的传统思想，如近似计算，可能有助于解决这一挑战。然而，引入这样的想法是不可能的，因为复杂的性能，功率和错误权衡源自独特的SFQ器件特性。这项工作介绍了近似的基于sfq的计算（AxSFQ）与架构建模框架和基本的设计准则。我们优化的器件级AxSFQ展示了30-100倍的能效提升，这激发了进一步的电路和架构级探索。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Approximate SFQ-Based Computing Architecture Modeling With Device-Level Guidelines

Single-flux-quantum (SFQ) logic has emerged as a promising post-Moore technology thanks to its ultra-fast and low-energy operation. However, despite progress in various fields, its feasibility is questionable due to the prohibitive cooling cost. Proven conventional ideas, such as approximate computing, may help to resolve this challenge. However, introducing such ideas has been impossible due to the complex performance, power, and error trade-offs originating from the unique SFQ device characteristics. This work introduces approximate SFQ-based computing (AxSFQ) with an architecture modeling framework and essential design guidelines. Our optimized device-level AxSFQ showcases 30–100 times energy efficiency improvement, which motivates further circuit and architecture-level exploration.

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.