Si/SiGe超晶格双栅反馈场效应晶体管及其在1T-DRAM中的应用

IF 1.9 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Subir Das, Ashraf Maniyar, Pushp Raj, Jawar Singh, Pramod Kumar Tiwari
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引用次数: 0

摘要

本文介绍了一种基于Si/SiGe超晶格的双栅反馈场效应晶体管(SL DGFBFET)的设计和性能分析。本文提出的SL DGFBFET是通过3nm薄Si层和Si1−x Gex层的堆叠而设计的,与基于Si的DGFBFET相比,具有更高的ON电流、更陡的开关特性和更大的存储窗口。该器件提供了19倍的ON电流(2.24 × 10−3 A/μm), 10.36倍的ION/IOFF比(~ 7.44 × 109), 1.7 V的大内存窗口和极低的亚阈值摆幅(~ 0.3 μV/decade),与类似尺寸的摩尔分数x = 0.4的si基FBFET相比,这对于记忆和神经形态应用非常有用。该器件的OFF-to-ON开关在较低的栅极电压(阈值电压= 0.34 V)下实现,使其适用于低功耗电子器件。我们还展示了所提出的器件在1T DRAM中的应用,在保持时间(~ 1000 s)和能耗(2.37 fJ/bit)方面表现出卓越的性能。本研究利用Synopsys TCAD工具进行器件结构设计和电性能分析。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Si/SiGe superlattice-based double gate feedback field-effect transistor and its application in 1T-DRAM
This work presents the design and performance analysis of a Si/SiGe superlattice-based double gate feedback field-effect transistor (SL DGFBFET). The proposed SL DGFBFET is designed successively by stacking 3 nm thin Si and Si1x Gex layers to achieve a higher ON current, extremely steeper switching characteristics, and a larger memory window than Si-based DGFBFET. The device offers 19 times higher ON current (2.24 × 10−3 A/μm), 10.36 times higher ION/IOFF ratio ( 7.44 × 109), a large memory window of 1.7 V, and an extremely lower subthreshold swing ( 0.3 μV/decade) than a Si-based FBFET of similar dimensions with a molar fraction x = 0.4, which can be very useful for memory and neuromorphic applications. The device’s OFF-to-ON switching is achieved at a lower gate voltage (threshold voltage = 0.34 V), making it suitable for low-power electronic devices. We have also shown the proposed device application in 1T DRAM which shows a remarkable performance in retention time ( 1000 s) and energy consumption (2.37 fJ/bit). The Synopsys TCAD tool has been utilized in the study to design the device structure and analyze its electrical performance.
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来源期刊
Microelectronics Journal
Microelectronics Journal 工程技术-工程:电子与电气
CiteScore
4.00
自引率
27.30%
发文量
222
审稿时长
43 days
期刊介绍: Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
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