Weizhong Chen , Zesheng Chen , Zhijie Deng , Yufan Xiao , Haishi Wang
{"title":"具有动态p阱控制和集成mos沟道二极管的双辅助栅SiC沟道MOSFET","authors":"Weizhong Chen , Zesheng Chen , Zhijie Deng , Yufan Xiao , Haishi Wang","doi":"10.1016/j.mejo.2025.106821","DOIUrl":null,"url":null,"abstract":"<div><div>An asymmetric trench SiC MOSFET featuring Double Auxiliary Gate (DAG-ATMOS) is proposed to enhance both forward conduction and reverse recovery performance. The Auxiliary Gate (AG) is inserted beside the Auxiliary Source (AS) in the P-well, and a P-type barrier region (P-re) controlled by AG is formed between AG and AS. During the on-state, AG and AS jointly completely deplete the P-re under a gate-to-source voltage (V<sub>GS</sub>) of 15 V, disconnecting the P-well from the source and leaving it floating. This reduces the JFET region resistance (R<sub>JFET</sub>). At the reverse conduction, AS introduces a low-barrier MOS-channel diode with a lower reverse conduction threshold voltage (V<sub>cut-in</sub>) compared with the body diode, effectively eliminating the bipolar degradation by suppressing the conduction of parasitic body diode. Simulation results show that the DAG-ATMOS demonstrates a specific on-resistance (R<sub>on,sp</sub>) of 2.64 mΩ cm<sup>2</sup> and R<sub>JFET</sub> of 0.94 mΩ cm<sup>2</sup>, representing reductions of 7.2 % and 16.8 %, respectively, compared to conventional ATMOS. The V<sub>cut-in</sub> of the DAG-ATMOS is 2.0 V, 0.8 V lower than the conventional structure, while the reverse recovery charge (Q<sub>RR</sub>) is reduced by 79.2 %.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106821"},"PeriodicalIF":1.9000,"publicationDate":"2025-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A double auxiliary gate SiC trench MOSFET with dynamic P-well control and integrated MOS-channel diode\",\"authors\":\"Weizhong Chen , Zesheng Chen , Zhijie Deng , Yufan Xiao , Haishi Wang\",\"doi\":\"10.1016/j.mejo.2025.106821\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>An asymmetric trench SiC MOSFET featuring Double Auxiliary Gate (DAG-ATMOS) is proposed to enhance both forward conduction and reverse recovery performance. The Auxiliary Gate (AG) is inserted beside the Auxiliary Source (AS) in the P-well, and a P-type barrier region (P-re) controlled by AG is formed between AG and AS. During the on-state, AG and AS jointly completely deplete the P-re under a gate-to-source voltage (V<sub>GS</sub>) of 15 V, disconnecting the P-well from the source and leaving it floating. This reduces the JFET region resistance (R<sub>JFET</sub>). At the reverse conduction, AS introduces a low-barrier MOS-channel diode with a lower reverse conduction threshold voltage (V<sub>cut-in</sub>) compared with the body diode, effectively eliminating the bipolar degradation by suppressing the conduction of parasitic body diode. Simulation results show that the DAG-ATMOS demonstrates a specific on-resistance (R<sub>on,sp</sub>) of 2.64 mΩ cm<sup>2</sup> and R<sub>JFET</sub> of 0.94 mΩ cm<sup>2</sup>, representing reductions of 7.2 % and 16.8 %, respectively, compared to conventional ATMOS. The V<sub>cut-in</sub> of the DAG-ATMOS is 2.0 V, 0.8 V lower than the conventional structure, while the reverse recovery charge (Q<sub>RR</sub>) is reduced by 79.2 %.</div></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":\"165 \",\"pages\":\"Article 106821\"},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2025-08-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S187923912500270X\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S187923912500270X","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A double auxiliary gate SiC trench MOSFET with dynamic P-well control and integrated MOS-channel diode
An asymmetric trench SiC MOSFET featuring Double Auxiliary Gate (DAG-ATMOS) is proposed to enhance both forward conduction and reverse recovery performance. The Auxiliary Gate (AG) is inserted beside the Auxiliary Source (AS) in the P-well, and a P-type barrier region (P-re) controlled by AG is formed between AG and AS. During the on-state, AG and AS jointly completely deplete the P-re under a gate-to-source voltage (VGS) of 15 V, disconnecting the P-well from the source and leaving it floating. This reduces the JFET region resistance (RJFET). At the reverse conduction, AS introduces a low-barrier MOS-channel diode with a lower reverse conduction threshold voltage (Vcut-in) compared with the body diode, effectively eliminating the bipolar degradation by suppressing the conduction of parasitic body diode. Simulation results show that the DAG-ATMOS demonstrates a specific on-resistance (Ron,sp) of 2.64 mΩ cm2 and RJFET of 0.94 mΩ cm2, representing reductions of 7.2 % and 16.8 %, respectively, compared to conventional ATMOS. The Vcut-in of the DAG-ATMOS is 2.0 V, 0.8 V lower than the conventional structure, while the reverse recovery charge (QRR) is reduced by 79.2 %.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
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