{"title":"具有优异的电气和物理性能的4双输入NAND栅极芯片的设计与制造。","authors":"Lijun Zhang, Wenqiang Dang, Yu Lu, Yongshun Wang","doi":"10.1038/s41598-025-14874-4","DOIUrl":null,"url":null,"abstract":"<p><p>In order to improve the performances of 4 two-input NAND so that it can be better used in the aerospace application field and in harsh environments, 4 two-input NAND gate chips were designed and successfully fabricated in this paper, based on 1.2 [Formula: see text]m P-well SPDM CMOS technological processes. The N transistors were fabricated in P-well and connected to GND via [Formula: see text]-well. The metal wires of [Formula: see text] use [Formula: see text] substrate to contact [Formula: see text], to increase its anti-locking capability. An ESD protection circuit was designed at the input terminals, prohibiting the terminal of IC chip from being damaged by ESD stress. The performance of the device is superior to that of other similar products in the world.</p>","PeriodicalId":21811,"journal":{"name":"Scientific Reports","volume":"15 1","pages":"29430"},"PeriodicalIF":3.9000,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.ncbi.nlm.nih.gov/pmc/articles/PMC12340108/pdf/","citationCount":"0","resultStr":"{\"title\":\"Design and fabrication of 4 double input NAND gate chip with excellent electrical and physical performances.\",\"authors\":\"Lijun Zhang, Wenqiang Dang, Yu Lu, Yongshun Wang\",\"doi\":\"10.1038/s41598-025-14874-4\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p><p>In order to improve the performances of 4 two-input NAND so that it can be better used in the aerospace application field and in harsh environments, 4 two-input NAND gate chips were designed and successfully fabricated in this paper, based on 1.2 [Formula: see text]m P-well SPDM CMOS technological processes. The N transistors were fabricated in P-well and connected to GND via [Formula: see text]-well. The metal wires of [Formula: see text] use [Formula: see text] substrate to contact [Formula: see text], to increase its anti-locking capability. An ESD protection circuit was designed at the input terminals, prohibiting the terminal of IC chip from being damaged by ESD stress. The performance of the device is superior to that of other similar products in the world.</p>\",\"PeriodicalId\":21811,\"journal\":{\"name\":\"Scientific Reports\",\"volume\":\"15 1\",\"pages\":\"29430\"},\"PeriodicalIF\":3.9000,\"publicationDate\":\"2025-08-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://www.ncbi.nlm.nih.gov/pmc/articles/PMC12340108/pdf/\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Scientific Reports\",\"FirstCategoryId\":\"103\",\"ListUrlMain\":\"https://doi.org/10.1038/s41598-025-14874-4\",\"RegionNum\":2,\"RegionCategory\":\"综合性期刊\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q1\",\"JCRName\":\"MULTIDISCIPLINARY SCIENCES\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Scientific Reports","FirstCategoryId":"103","ListUrlMain":"https://doi.org/10.1038/s41598-025-14874-4","RegionNum":2,"RegionCategory":"综合性期刊","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"MULTIDISCIPLINARY SCIENCES","Score":null,"Total":0}
引用次数: 0
摘要
为了提高4双输入NAND的性能,使其能够更好地应用于航空航天应用领域和恶劣环境中,本文基于1.2 m P-well SPDM CMOS工艺流程,设计并成功制造了4个双输入NAND栅极芯片。N个晶体管在p孔中制造,并通过[公式:见文本]-孔连接到GND。【公式:见文】的金属导线利用【公式:见文】基材与【公式:见文】接触,增加其防抱死能力。在输入端设计ESD保护电路,防止IC芯片端子受到ESD应力的破坏。该装置的性能优于国际同类产品。
Design and fabrication of 4 double input NAND gate chip with excellent electrical and physical performances.
In order to improve the performances of 4 two-input NAND so that it can be better used in the aerospace application field and in harsh environments, 4 two-input NAND gate chips were designed and successfully fabricated in this paper, based on 1.2 [Formula: see text]m P-well SPDM CMOS technological processes. The N transistors were fabricated in P-well and connected to GND via [Formula: see text]-well. The metal wires of [Formula: see text] use [Formula: see text] substrate to contact [Formula: see text], to increase its anti-locking capability. An ESD protection circuit was designed at the input terminals, prohibiting the terminal of IC chip from being damaged by ESD stress. The performance of the device is superior to that of other similar products in the world.
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