Efficient address generator architectures for IEEE 802.16e WiMAX deinterleaver based on SPAM approach

This paper presents a VLSI implementation of a Synchronous Pipelined Array Multiplier (SPAM)-based address generation architecture designed for a WiMAX deinterleaver. The proposed design enhances throughput and reduces latency by adding parallelism within the array multiplier, specifically designed for efficient WiMAX deinterleaver. The architecture maintains synchronization with WiMAX operations and focuses on low power consumption, making it compatible for integration into energy-efficient systems. Simulation results demonstrate superior performance in terms of speed, power efficiency, and throughput, highlighting the architecture's suitability for high-performance WiMAX systems, particularly in wireless broadband communication. The proposed SPAM-based address generator is 58% and 18% faster than LUT-based and MUX-based systems, respectively. It also achieves 45% and 15% lower power consumption, respectively. Implemented in 45 nm CMOS technology, the proposed multiplier better performs the LUT-based architecture in Power-Delay Product (PDP) and Area-Delay Product (ADP) by 71% and 37%, respectively.